1 /* 2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3036_H 7 #define _ASM_ARCH_CRU_RK3036_H 8 9 #include <common.h> 10 11 #define OSC_HZ (24 * 1000 * 1000) 12 13 #define APLL_HZ (600 * 1000000) 14 #define GPLL_HZ (594 * 1000000) 15 16 #define CORE_PERI_HZ 150000000 17 #define CORE_ACLK_HZ 300000000 18 19 #define BUS_ACLK_HZ 148500000 20 #define BUS_HCLK_HZ 148500000 21 #define BUS_PCLK_HZ 74250000 22 23 #define PERI_ACLK_HZ 148500000 24 #define PERI_HCLK_HZ 148500000 25 #define PERI_PCLK_HZ 74250000 26 27 /* Private data for the clock driver - used by rockchip_get_cru() */ 28 struct rk3036_clk_priv { 29 struct rk3036_cru *cru; 30 ulong rate; 31 }; 32 33 struct rk3036_cru { 34 struct rk3036_pll { 35 unsigned int con0; 36 unsigned int con1; 37 unsigned int con2; 38 unsigned int con3; 39 } pll[4]; 40 unsigned int cru_mode_con; 41 unsigned int cru_clksel_con[35]; 42 unsigned int cru_clkgate_con[11]; 43 unsigned int reserved; 44 unsigned int cru_glb_srst_fst_value; 45 unsigned int cru_glb_srst_snd_value; 46 unsigned int reserved1[2]; 47 unsigned int cru_softrst_con[9]; 48 unsigned int cru_misc_con; 49 unsigned int reserved2[2]; 50 unsigned int cru_glb_cnt_th; 51 unsigned int cru_sdmmc_con[2]; 52 unsigned int cru_sdio_con[2]; 53 unsigned int cru_emmc_con[2]; 54 unsigned int reserved3; 55 unsigned int cru_rst_st; 56 unsigned int reserved4[0x23]; 57 unsigned int cru_pll_mask_con; 58 }; 59 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); 60 61 struct pll_div { 62 u32 refdiv; 63 u32 fbdiv; 64 u32 postdiv1; 65 u32 postdiv2; 66 u32 frac; 67 }; 68 69 enum { 70 /* PLLCON0*/ 71 PLL_POSTDIV1_SHIFT = 12, 72 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 73 PLL_FBDIV_SHIFT = 0, 74 PLL_FBDIV_MASK = 0xfff, 75 76 /* PLLCON1 */ 77 PLL_RST_SHIFT = 14, 78 PLL_PD_SHIFT = 13, 79 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 80 PLL_DSMPD_SHIFT = 12, 81 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 82 PLL_LOCK_STATUS_SHIFT = 10, 83 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 84 PLL_POSTDIV2_SHIFT = 6, 85 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 86 PLL_REFDIV_SHIFT = 0, 87 PLL_REFDIV_MASK = 0x3f, 88 89 /* CRU_MODE */ 90 GPLL_MODE_SHIFT = 12, 91 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 92 GPLL_MODE_SLOW = 0, 93 GPLL_MODE_NORM, 94 GPLL_MODE_DEEP, 95 DPLL_MODE_SHIFT = 4, 96 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 97 DPLL_MODE_SLOW = 0, 98 DPLL_MODE_NORM, 99 APLL_MODE_SHIFT = 0, 100 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 101 APLL_MODE_SLOW = 0, 102 APLL_MODE_NORM, 103 104 /* CRU_CLK_SEL0_CON */ 105 BUS_ACLK_PLL_SEL_SHIFT = 14, 106 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 107 BUS_ACLK_PLL_SEL_APLL = 0, 108 BUS_ACLK_PLL_SEL_DPLL, 109 BUS_ACLK_PLL_SEL_GPLL, 110 BUS_ACLK_DIV_SHIFT = 8, 111 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 112 CORE_CLK_PLL_SEL_SHIFT = 7, 113 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 114 CORE_CLK_PLL_SEL_APLL = 0, 115 CORE_CLK_PLL_SEL_GPLL, 116 CORE_DIV_CON_SHIFT = 0, 117 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 118 119 /* CRU_CLK_SEL1_CON */ 120 BUS_PCLK_DIV_SHIFT = 12, 121 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 122 BUS_HCLK_DIV_SHIFT = 8, 123 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 124 CORE_ACLK_DIV_SHIFT = 4, 125 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 126 CORE_PERI_DIV_SHIFT = 0, 127 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 128 129 /* CRU_CLKSEL10_CON */ 130 PERI_PLL_SEL_SHIFT = 14, 131 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 132 PERI_PLL_APLL = 0, 133 PERI_PLL_DPLL, 134 PERI_PLL_GPLL, 135 PERI_PCLK_DIV_SHIFT = 12, 136 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 137 PERI_HCLK_DIV_SHIFT = 8, 138 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 139 PERI_ACLK_DIV_SHIFT = 0, 140 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 141 142 /* CRU_CLKSEL11_CON */ 143 SDIO_DIV_SHIFT = 8, 144 SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, 145 MMC0_DIV_SHIFT = 0, 146 MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, 147 148 /* CRU_CLKSEL12_CON */ 149 EMMC_PLL_SHIFT = 12, 150 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 151 EMMC_SEL_APLL = 0, 152 EMMC_SEL_DPLL, 153 EMMC_SEL_GPLL, 154 EMMC_SEL_24M, 155 SDIO_PLL_SHIFT = 10, 156 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 157 SDIO_SEL_APLL = 0, 158 SDIO_SEL_DPLL, 159 SDIO_SEL_GPLL, 160 SDIO_SEL_24M, 161 MMC0_PLL_SHIFT = 8, 162 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 163 MMC0_SEL_APLL = 0, 164 MMC0_SEL_DPLL, 165 MMC0_SEL_GPLL, 166 MMC0_SEL_24M, 167 EMMC_DIV_SHIFT = 0, 168 EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, 169 170 /* CRU_SOFTRST5_CON */ 171 DDRCTRL_PSRST_SHIFT = 11, 172 DDRCTRL_SRST_SHIFT = 10, 173 DDRPHY_PSRST_SHIFT = 9, 174 DDRPHY_SRST_SHIFT = 8, 175 }; 176 #endif 177