xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-pxa/regs-uart.h (revision 326ea986ac150acdc7656d57fca647db80b50158)
1237ce0feSMarek Vasut /*
2237ce0feSMarek Vasut  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
3237ce0feSMarek Vasut  *
4*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5237ce0feSMarek Vasut  */
6237ce0feSMarek Vasut 
7237ce0feSMarek Vasut #ifndef	__REGS_UART_H__
8237ce0feSMarek Vasut #define	__REGS_UART_H__
9237ce0feSMarek Vasut 
10237ce0feSMarek Vasut #define	FFUART_BASE		0x40100000
11237ce0feSMarek Vasut #define	BTUART_BASE		0x40200000
12237ce0feSMarek Vasut #define	STUART_BASE		0x40700000
13237ce0feSMarek Vasut #define	HWUART_BASE		0x41600000
14237ce0feSMarek Vasut 
15237ce0feSMarek Vasut struct pxa_uart_regs {
16237ce0feSMarek Vasut 	union {
17237ce0feSMarek Vasut 		uint32_t	thr;
18237ce0feSMarek Vasut 		uint32_t	rbr;
19237ce0feSMarek Vasut 		uint32_t	dll;
20237ce0feSMarek Vasut 	};
21237ce0feSMarek Vasut 	union {
22237ce0feSMarek Vasut 		uint32_t	ier;
23237ce0feSMarek Vasut 		uint32_t	dlh;
24237ce0feSMarek Vasut 	};
25237ce0feSMarek Vasut 	union {
26237ce0feSMarek Vasut 		uint32_t	fcr;
27237ce0feSMarek Vasut 		uint32_t	iir;
28237ce0feSMarek Vasut 	};
29237ce0feSMarek Vasut 	uint32_t	lcr;
30237ce0feSMarek Vasut 	uint32_t	mcr;
31237ce0feSMarek Vasut 	uint32_t	lsr;
32237ce0feSMarek Vasut 	uint32_t	msr;
33237ce0feSMarek Vasut 	uint32_t	spr;
34237ce0feSMarek Vasut 	uint32_t	isr;
35237ce0feSMarek Vasut };
36237ce0feSMarek Vasut 
37237ce0feSMarek Vasut #define	IER_DMAE	(1 << 7)
38237ce0feSMarek Vasut #define	IER_UUE		(1 << 6)
39237ce0feSMarek Vasut #define	IER_NRZE	(1 << 5)
40237ce0feSMarek Vasut #define	IER_RTIOE	(1 << 4)
41237ce0feSMarek Vasut #define	IER_MIE		(1 << 3)
42237ce0feSMarek Vasut #define	IER_RLSE	(1 << 2)
43237ce0feSMarek Vasut #define	IER_TIE		(1 << 1)
44237ce0feSMarek Vasut #define	IER_RAVIE	(1 << 0)
45237ce0feSMarek Vasut 
46237ce0feSMarek Vasut #define	IIR_FIFOES1	(1 << 7)
47237ce0feSMarek Vasut #define	IIR_FIFOES0	(1 << 6)
48237ce0feSMarek Vasut #define	IIR_TOD		(1 << 3)
49237ce0feSMarek Vasut #define	IIR_IID2	(1 << 2)
50237ce0feSMarek Vasut #define	IIR_IID1	(1 << 1)
51237ce0feSMarek Vasut #define	IIR_IP		(1 << 0)
52237ce0feSMarek Vasut 
53237ce0feSMarek Vasut #define	FCR_ITL2	(1 << 7)
54237ce0feSMarek Vasut #define	FCR_ITL1	(1 << 6)
55237ce0feSMarek Vasut #define	FCR_RESETTF	(1 << 2)
56237ce0feSMarek Vasut #define	FCR_RESETRF	(1 << 1)
57237ce0feSMarek Vasut #define	FCR_TRFIFOE	(1 << 0)
58237ce0feSMarek Vasut #define	FCR_ITL_1	0
59237ce0feSMarek Vasut #define	FCR_ITL_8	(FCR_ITL1)
60237ce0feSMarek Vasut #define	FCR_ITL_16	(FCR_ITL2)
61237ce0feSMarek Vasut #define	FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
62237ce0feSMarek Vasut 
63237ce0feSMarek Vasut #define	LCR_DLAB	(1 << 7)
64237ce0feSMarek Vasut #define	LCR_SB		(1 << 6)
65237ce0feSMarek Vasut #define	LCR_STKYP	(1 << 5)
66237ce0feSMarek Vasut #define	LCR_EPS		(1 << 4)
67237ce0feSMarek Vasut #define	LCR_PEN		(1 << 3)
68237ce0feSMarek Vasut #define	LCR_STB		(1 << 2)
69237ce0feSMarek Vasut #define	LCR_WLS1	(1 << 1)
70237ce0feSMarek Vasut #define	LCR_WLS0	(1 << 0)
71237ce0feSMarek Vasut 
72237ce0feSMarek Vasut #define	LSR_FIFOE	(1 << 7)
73237ce0feSMarek Vasut #define	LSR_TEMT	(1 << 6)
74237ce0feSMarek Vasut #define	LSR_TDRQ	(1 << 5)
75237ce0feSMarek Vasut #define	LSR_BI		(1 << 4)
76237ce0feSMarek Vasut #define	LSR_FE		(1 << 3)
77237ce0feSMarek Vasut #define	LSR_PE		(1 << 2)
78237ce0feSMarek Vasut #define	LSR_OE		(1 << 1)
79237ce0feSMarek Vasut #define	LSR_DR		(1 << 0)
80237ce0feSMarek Vasut 
81237ce0feSMarek Vasut #define	MCR_LOOP	(1 << 4)
82237ce0feSMarek Vasut #define	MCR_OUT2	(1 << 3)
83237ce0feSMarek Vasut #define	MCR_OUT1	(1 << 2)
84237ce0feSMarek Vasut #define	MCR_RTS		(1 << 1)
85237ce0feSMarek Vasut #define	MCR_DTR		(1 << 0)
86237ce0feSMarek Vasut 
87237ce0feSMarek Vasut #define	MSR_DCD		(1 << 7)
88237ce0feSMarek Vasut #define	MSR_RI		(1 << 6)
89237ce0feSMarek Vasut #define	MSR_DSR		(1 << 5)
90237ce0feSMarek Vasut #define	MSR_CTS		(1 << 4)
91237ce0feSMarek Vasut #define	MSR_DDCD	(1 << 3)
92237ce0feSMarek Vasut #define	MSR_TERI	(1 << 2)
93237ce0feSMarek Vasut #define	MSR_DDSR	(1 << 1)
94237ce0feSMarek Vasut #define	MSR_DCTS	(1 << 0)
95237ce0feSMarek Vasut 
96237ce0feSMarek Vasut #endif	/* __REGS_UART_H__ */
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