1*a087a7fbSRoger Quadros /* 2*a087a7fbSRoger Quadros * SATA Wrapper Register map 3*a087a7fbSRoger Quadros * 4*a087a7fbSRoger Quadros * (C) Copyright 2013 5*a087a7fbSRoger Quadros * Texas Instruments, <www.ti.com> 6*a087a7fbSRoger Quadros * 7*a087a7fbSRoger Quadros * SPDX-License-Identifier: GPL-2.0+ 8*a087a7fbSRoger Quadros */ 9*a087a7fbSRoger Quadros 10*a087a7fbSRoger Quadros #ifndef _TI_SATA_H 11*a087a7fbSRoger Quadros #define _TI_SATA_H 12*a087a7fbSRoger Quadros 13*a087a7fbSRoger Quadros /* SATA Wrapper module */ 14*a087a7fbSRoger Quadros #define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) 15*a087a7fbSRoger Quadros /* SATA PHY Module */ 16*a087a7fbSRoger Quadros #define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) 17*a087a7fbSRoger Quadros 18*a087a7fbSRoger Quadros /* SATA Wrapper register offsets */ 19*a087a7fbSRoger Quadros #define TI_SATA_SYSCONFIG 0x00 20*a087a7fbSRoger Quadros #define TI_SATA_CDRLOCK 0x04 21*a087a7fbSRoger Quadros 22*a087a7fbSRoger Quadros /* Register Set */ 23*a087a7fbSRoger Quadros #define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) 24*a087a7fbSRoger Quadros #define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) 25*a087a7fbSRoger Quadros #define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) 26*a087a7fbSRoger Quadros 27*a087a7fbSRoger Quadros /* Standby modes */ 28*a087a7fbSRoger Quadros #define TI_SATA_STANDBY_FORCE 0x0 29*a087a7fbSRoger Quadros #define TI_SATA_STANDBY_NO (0x1 << 4) 30*a087a7fbSRoger Quadros #define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) 31*a087a7fbSRoger Quadros #define TI_SATA_STANDBY_SMART (0x2 << 4) 32*a087a7fbSRoger Quadros 33*a087a7fbSRoger Quadros /* Idle modes */ 34*a087a7fbSRoger Quadros #define TI_SATA_IDLE_FORCE 0x0 35*a087a7fbSRoger Quadros #define TI_SATA_IDLE_NO (0x1 << 2) 36*a087a7fbSRoger Quadros #define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) 37*a087a7fbSRoger Quadros #define TI_SATA_IDLE_SMART (0x2 << 2) 38*a087a7fbSRoger Quadros 39*a087a7fbSRoger Quadros #endif /* _TI_SATA_H */ 40