1cd324a6dSpekon gupta /* 2cd324a6dSpekon gupta * (C) Copyright 2006-2008 3cd324a6dSpekon gupta * Texas Instruments, <www.ti.com> 4cd324a6dSpekon gupta * 5cd324a6dSpekon gupta * Author 6cd324a6dSpekon gupta * Mansoor Ahamed <mansoor.ahamed@ti.com> 7cd324a6dSpekon gupta * 8cd324a6dSpekon gupta * Initial Code from: 9cd324a6dSpekon gupta * Richard Woodruff <r-woodruff2@ti.com> 10cd324a6dSpekon gupta * 11cd324a6dSpekon gupta * SPDX-License-Identifier: GPL-2.0+ 12cd324a6dSpekon gupta */ 13cd324a6dSpekon gupta 14cd324a6dSpekon gupta #ifndef _MEM_H_ 15cd324a6dSpekon gupta #define _MEM_H_ 16cd324a6dSpekon gupta 17cd324a6dSpekon gupta /* 18cd324a6dSpekon gupta * GPMC settings - 19cd324a6dSpekon gupta * Definitions is as per the following format 20cd324a6dSpekon gupta * #define <PART>_GPMC_CONFIG<x> <value> 21cd324a6dSpekon gupta * Where: 22cd324a6dSpekon gupta * PART is the part name e.g. STNOR - Intel Strata Flash 23cd324a6dSpekon gupta * x is GPMC config registers from 1 to 6 (there will be 6 macros) 24cd324a6dSpekon gupta * Value is corresponding value 25cd324a6dSpekon gupta * 26cd324a6dSpekon gupta * For every valid PRCM configuration there should be only one definition of 27cd324a6dSpekon gupta * the same. if values are independent of the board, this definition will be 28cd324a6dSpekon gupta * present in this file if values are dependent on the board, then this should 29cd324a6dSpekon gupta * go into corresponding mem-boardName.h file 30cd324a6dSpekon gupta * 31cd324a6dSpekon gupta * Currently valid part Names are (PART): 32cd324a6dSpekon gupta * M_NAND - Micron NAND 33cd324a6dSpekon gupta * STNOR - STMicrolelctronics M29W128GL 34cd324a6dSpekon gupta */ 35cd324a6dSpekon gupta #define GPMC_SIZE_256M 0x0 36cd324a6dSpekon gupta #define GPMC_SIZE_128M 0x8 37cd324a6dSpekon gupta #define GPMC_SIZE_64M 0xC 38cd324a6dSpekon gupta #define GPMC_SIZE_32M 0xE 39cd324a6dSpekon gupta #define GPMC_SIZE_16M 0xF 40cd324a6dSpekon gupta 41cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG1 0x00000800 42cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG2 0x001e1e00 43cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG3 0x001e1e00 44cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG4 0x16051807 45cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG5 0x00151e1e 46cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG6 0x16000f80 47cd324a6dSpekon gupta #define M_NAND_GPMC_CONFIG7 0x00000008 48cd324a6dSpekon gupta 49*9352697aSpekon gupta #define STNOR_GPMC_CONFIG1 0x00001000 50*9352697aSpekon gupta #define STNOR_GPMC_CONFIG2 0x001f1f00 51*9352697aSpekon gupta #define STNOR_GPMC_CONFIG3 0x001f1f01 52*9352697aSpekon gupta #define STNOR_GPMC_CONFIG4 0x1f011f01 53*9352697aSpekon gupta #define STNOR_GPMC_CONFIG5 0x001d1f1f 54cd324a6dSpekon gupta #define STNOR_GPMC_CONFIG6 0x08070280 55*9352697aSpekon gupta #define STNOR_GPMC_CONFIG7 0x00000048 56cd324a6dSpekon gupta 57cd324a6dSpekon gupta /* max number of GPMC Chip Selects */ 58cd324a6dSpekon gupta #define GPMC_MAX_CS 8 59cd324a6dSpekon gupta /* max number of GPMC regs */ 60cd324a6dSpekon gupta #define GPMC_MAX_REG 7 61cd324a6dSpekon gupta 62cd324a6dSpekon gupta #endif /* endif _MEM_H_ */ 63