1d34efc76SSteve Sakoman /* 2d34efc76SSteve Sakoman * (C) Copyright 2010 3d34efc76SSteve Sakoman * Texas Instruments, <www.ti.com> 4d34efc76SSteve Sakoman * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6d34efc76SSteve Sakoman */ 7d34efc76SSteve Sakoman 8d34efc76SSteve Sakoman #ifndef _SYS_PROTO_H_ 9d34efc76SSteve Sakoman #define _SYS_PROTO_H_ 10d34efc76SSteve Sakoman 11508a58faSSricharan #include <asm/arch/omap.h> 12af1d002fSLokesh Vutla #include <asm/arch/clock.h> 13d34efc76SSteve Sakoman #include <asm/io.h> 14d2f18c27SAneesh V #include <asm/omap_common.h> 156aff0509Spekon gupta #include <linux/mtd/omap_gpmc.h> 16469ec1e3SAneesh V #include <asm/arch/mux_omap4.h> 17939911a6STom Rini #include <asm/ti-common/sys_proto.h> 18d34efc76SSteve Sakoman 194a0eb757SSRICHARAN R DECLARE_GLOBAL_DATA_PTR; 204a0eb757SSRICHARAN R 21675cc77aSHardik Patel extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; 22675cc77aSHardik Patel extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; 23675cc77aSHardik Patel extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; 24675cc77aSHardik Patel extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; 2538e5a5abSNishanth Menon extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; 2638e5a5abSNishanth Menon extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; 2738e5a5abSNishanth Menon extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; 28d34efc76SSteve Sakoman struct omap_sysinfo { 29d34efc76SSteve Sakoman char *board_string; 30d34efc76SSteve Sakoman }; 31d2f18c27SAneesh V extern const struct omap_sysinfo sysinfo; 32d34efc76SSteve Sakoman 3327952014SSteve Sakoman void gpmc_init(void); 34d34efc76SSteve Sakoman void watchdog_init(void); 35d34efc76SSteve Sakoman u32 get_device_type(void); 36469ec1e3SAneesh V void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); 37508a58faSSricharan void set_muxconf_regs_essential(void); 380e7b6217SSteve Sakoman u32 wait_on_value(u32, u32, void *, u32); 390e7b6217SSteve Sakoman void sdelay(unsigned long); 4093e6253dSKipisz, Steven void setup_early_clocks(void); 413776801dSAneesh V void prcm_init(void); 42*d88d6c8cSKipisz, Steven void do_board_detect(void); 4301b753ffSSRICHARAN R void bypass_dpll(u32 const base); 443776801dSAneesh V void freq_update_core(void); 453776801dSAneesh V u32 get_sys_clk_freq(void); 463776801dSAneesh V u32 omap4_ddr_clk(void); 47095aea29SAneesh V void cancel_out(u32 *num, u32 *den, u32 den_limit); 482ae610f0SAneesh V void sdram_init(void); 49508a58faSSricharan u32 omap_sdram_size(void); 50508a58faSSricharan u32 cortex_rev(void); 514596dcc1STom Rini void save_omap_boot_params(void); 52508a58faSSricharan void init_omap_revision(void); 53508a58faSSricharan void do_io_settings(void); 544ca94d81SLokesh Vutla void sri2c_init(void); 55a78274b2SNishanth Menon int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); 5670239507SLokesh Vutla u32 warm_reset(void); 5738f25b12SLokesh Vutla void force_emif_self_refresh(void); 580b1b60c7SLokesh Vutla void setup_warmreset_time(void); 596d8abe6aSNishanth Menon 606d8abe6aSNishanth Menon #define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 616d8abe6aSNishanth Menon 62d34efc76SSteve Sakoman #endif 63