1*e4426d07Spekon gupta /* 2*e4426d07Spekon gupta * (C) Copyright 2006-2008 3*e4426d07Spekon gupta * Texas Instruments, <www.ti.com> 4*e4426d07Spekon gupta * 5*e4426d07Spekon gupta * Author 6*e4426d07Spekon gupta * Mansoor Ahamed <mansoor.ahamed@ti.com> 7*e4426d07Spekon gupta * 8*e4426d07Spekon gupta * Initial Code from: 9*e4426d07Spekon gupta * Richard Woodruff <r-woodruff2@ti.com> 10*e4426d07Spekon gupta * 11*e4426d07Spekon gupta * SPDX-License-Identifier: GPL-2.0+ 12*e4426d07Spekon gupta */ 13*e4426d07Spekon gupta 14*e4426d07Spekon gupta #ifndef _MEM_H_ 15*e4426d07Spekon gupta #define _MEM_H_ 16*e4426d07Spekon gupta 17*e4426d07Spekon gupta /* 18*e4426d07Spekon gupta * GPMC settings - 19*e4426d07Spekon gupta * Definitions is as per the following format 20*e4426d07Spekon gupta * #define <PART>_GPMC_CONFIG<x> <value> 21*e4426d07Spekon gupta * Where: 22*e4426d07Spekon gupta * PART is the part name e.g. STNOR - Intel Strata Flash 23*e4426d07Spekon gupta * x is GPMC config registers from 1 to 6 (there will be 6 macros) 24*e4426d07Spekon gupta * Value is corresponding value 25*e4426d07Spekon gupta * 26*e4426d07Spekon gupta * For every valid PRCM configuration there should be only one definition of 27*e4426d07Spekon gupta * the same. if values are independent of the board, this definition will be 28*e4426d07Spekon gupta * present in this file if values are dependent on the board, then this should 29*e4426d07Spekon gupta * go into corresponding mem-boardName.h file 30*e4426d07Spekon gupta * 31*e4426d07Spekon gupta * Currently valid part Names are (PART): 32*e4426d07Spekon gupta * M_NAND - Micron NAND 33*e4426d07Spekon gupta * STNOR - STMicrolelctronics M29W128GL 34*e4426d07Spekon gupta */ 35*e4426d07Spekon gupta #define GPMC_SIZE_256M 0x0 36*e4426d07Spekon gupta #define GPMC_SIZE_128M 0x8 37*e4426d07Spekon gupta #define GPMC_SIZE_64M 0xC 38*e4426d07Spekon gupta #define GPMC_SIZE_32M 0xE 39*e4426d07Spekon gupta #define GPMC_SIZE_16M 0xF 40*e4426d07Spekon gupta 41*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG1 0x00000800 42*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG2 0x001e1e00 43*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG3 0x001e1e00 44*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG4 0x16051807 45*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG5 0x00151e1e 46*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG6 0x16000f80 47*e4426d07Spekon gupta #define M_NAND_GPMC_CONFIG7 0x00000008 48*e4426d07Spekon gupta 49*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG1 0x00001200 50*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG2 0x00101000 51*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG3 0x00030301 52*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG4 0x10041004 53*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG5 0x000C1010 54*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG6 0x08070280 55*e4426d07Spekon gupta #define STNOR_GPMC_CONFIG7 0x00000F48 56*e4426d07Spekon gupta 57*e4426d07Spekon gupta /* max number of GPMC Chip Selects */ 58*e4426d07Spekon gupta #define GPMC_MAX_CS 8 59*e4426d07Spekon gupta /* max number of GPMC regs */ 60*e4426d07Spekon gupta #define GPMC_MAX_REG 7 61*e4426d07Spekon gupta 62*e4426d07Spekon gupta #endif /* endif _MEM_H_ */ 63