1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _MEM_H_ 26 #define _MEM_H_ 27 28 #define CS0 0x0 29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31 #ifndef __ASSEMBLY__ 32 enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37 }; 38 #endif /* __ASSEMBLY__ */ 39 40 #define EARLY_INIT 1 41 42 /* Slower full frequency range default timings for x32 operation*/ 43 #define SDRC_SHARING 0x00000100 44 #define SDRC_MR_0_SDR 0x00000031 45 46 #define DLL_OFFSET 0 47 #define DLL_WRITEDDRCLKX2DIS 1 48 #define DLL_ENADLL 1 49 #define DLL_LOCKDLL 0 50 #define DLL_DLLPHASE_72 0 51 #define DLL_DLLPHASE_90 1 52 53 /* rkw - need to find of 90/72 degree recommendation for speed like before */ 54 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56 57 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 58 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 59 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 60 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 61 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 62 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 63 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 64 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 65 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 66 67 #define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \ 68 ACTIM_CTRLA_TRFC(a) | \ 69 ACTIM_CTRLA_TRC(b) | \ 70 ACTIM_CTRLA_TRAS(b) | \ 71 ACTIM_CTRLA_TRP(d) | \ 72 ACTIM_CTRLA_TRCD(e) | \ 73 ACTIM_CTRLA_TRRD(f) | \ 74 ACTIM_CTRLA_TDPL(g) | \ 75 ACTIM_CTRLA_TDAL(h) 76 77 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 78 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 79 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 80 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 81 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 82 83 #define ACTIM_CTRLB(a,b,c,d) \ 84 ACTIM_CTRLB_TWTR(a) | \ 85 ACTIM_CTRLB_TCKE(b) | \ 86 ACTIM_CTRLB_TXP(b) | \ 87 ACTIM_CTRLB_TXSR(d) 88 89 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns 90 * ACTIMA 91 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 92 * TDPL (Twr) = 15/6 = 2.5 -> 3 93 * TRRD = 12/6 = 2 94 * TRCD = 18/6 = 3 95 * TRP = 18/6 = 3 96 * TRAS = 42/6 = 7 97 * TRC = 60/6 = 10 98 * TRFC = 72/6 = 12 99 * ACTIMB 100 * TCKE = 2 101 * XSR = 120/6 = 20 102 */ 103 #define INFINEON_TDAL_165 6 104 #define INFINEON_TDPL_165 3 105 #define INFINEON_TRRD_165 2 106 #define INFINEON_TRCD_165 3 107 #define INFINEON_TRP_165 3 108 #define INFINEON_TRAS_165 7 109 #define INFINEON_TRC_165 10 110 #define INFINEON_TRFC_165 12 111 112 #define INFINEON_V_ACTIMA_165 \ 113 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 114 INFINEON_TRAS_165, INFINEON_TRP_165, \ 115 INFINEON_TRCD_165, INFINEON_TRRD_165, \ 116 INFINEON_TDPL_165, INFINEON_TDAL_165) 117 118 #define INFINEON_TWTR_165 1 119 #define INFINEON_TCKE_165 2 120 #define INFINEON_TXP_165 2 121 #define INFINEON_XSR_165 20 122 123 #define INFINEON_V_ACTIMB_165 \ 124 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 125 INFINEON_TXP_165, INFINEON_XSR_165) 126 127 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns 128 * ACTIMA 129 * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 130 * TDPL (Twr) = 15/6 = 2.5 -> 3 131 * TRRD = 12/6 = 2 132 * TRCD = 18/6 = 3 133 * TRP = 18/6 = 3 134 * TRAS = 42/6 = 7 135 * TRC = 60/6 = 10 136 * TRFC = 125/6 = 21 137 * ACTIMB 138 * TWTR = 1 139 * TCKE = 1 140 * TXSR = 138/6 = 23 141 * TXP = 25/6 = 4.1 ~5 142 */ 143 #define MICRON_TDAL_165 6 144 #define MICRON_TDPL_165 3 145 #define MICRON_TRRD_165 2 146 #define MICRON_TRCD_165 3 147 #define MICRON_TRP_165 3 148 #define MICRON_TRAS_165 7 149 #define MICRON_TRC_165 10 150 #define MICRON_TRFC_165 21 151 152 #define MICRON_V_ACTIMA_165 \ 153 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 154 MICRON_TRAS_165, MICRON_TRP_165, \ 155 MICRON_TRCD_165, MICRON_TRRD_165, \ 156 MICRON_TDPL_165, MICRON_TDAL_165) 157 158 #define MICRON_TWTR_165 1 159 #define MICRON_TCKE_165 1 160 #define MICRON_XSR_165 23 161 #define MICRON_TXP_165 5 162 163 #define MICRON_V_ACTIMB_165 \ 164 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 165 MICRON_TXP_165, MICRON_XSR_165) 166 167 #define MICRON_RAMTYPE 0x1 168 #define MICRON_DDRTYPE 0x0 169 #define MICRON_DEEPPD 0x1 170 #define MICRON_B32NOT16 0x1 171 #define MICRON_BANKALLOCATION 0x2 172 #define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) 173 #define MICRON_ADDRMUXLEGACY 0x1 174 #define MICRON_CASWIDTH 0x5 175 #define MICRON_RASWIDTH 0x2 176 #define MICRON_LOCKSTATUS 0x0 177 #define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ 178 (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ 179 (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ 180 (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ 181 (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) 182 183 #define MICRON_ARCV 2030 184 #define MICRON_ARE 0x1 185 #define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) 186 187 #define MICRON_BL 0x2 188 #define MICRON_SIL 0x0 189 #define MICRON_CASL 0x3 190 #define MICRON_WBST 0x0 191 #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ 192 (MICRON_SIL << 3) | (MICRON_BL)) 193 194 /* 195 * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns 196 * ACTIMA 197 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 198 * TDPL (Twr) = 15/6 = 2.5 -> 3 199 * TRRD = 12/6 = 2 200 * TRCD = 22.5/6 = 3.75 -> 4 201 * TRP = 18/6 = 3 202 * TRAS = 42/6 = 7 203 * TRC = 60/6 = 10 204 * TRFC = 140/6 = 23.3 -> 24 205 * ACTIMB 206 * TWTR = 2 207 * TCKE = 2 208 * TXSR = 200/6 = 33.3 -> 34 209 * TXP = 1.0 + 1.1 = 2.1 -> 3 210 */ 211 #define NUMONYX_TDAL_165 6 212 #define NUMONYX_TDPL_165 3 213 #define NUMONYX_TRRD_165 2 214 #define NUMONYX_TRCD_165 4 215 #define NUMONYX_TRP_165 3 216 #define NUMONYX_TRAS_165 7 217 #define NUMONYX_TRC_165 10 218 #define NUMONYX_TRFC_165 24 219 220 #define NUMONYX_V_ACTIMA_165 \ 221 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 222 NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 223 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 224 NUMONYX_TDPL_165, NUMONYX_TDAL_165) 225 226 #define NUMONYX_TWTR_165 2 227 #define NUMONYX_TCKE_165 2 228 #define NUMONYX_TXP_165 3 229 #define NUMONYX_XSR_165 34 230 231 #define NUMONYX_V_ACTIMB_165 \ 232 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 233 NUMONYX_TXP_165, NUMONYX_XSR_165) 234 235 #ifdef CONFIG_OMAP3_INFINEON_DDR 236 #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 237 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165 238 #endif 239 240 #ifdef CONFIG_OMAP3_MICRON_DDR 241 #define V_ACTIMA_165 MICRON_V_ACTIMA_165 242 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 243 #define V_MCFG MICRON_V_MCFG 244 #define V_RFR_CTRL MICRON_V_RFR_CTRL 245 #define V_MR MICRON_V_MR 246 #endif 247 248 #ifdef CONFIG_OMAP3_NUMONYX_DDR 249 #define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 250 #define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 251 #endif 252 253 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 254 #error "Please choose the right DDR type in config header" 255 #endif 256 257 #if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) 258 #error "Please choose the right DDR type in config header" 259 #endif 260 261 /* 262 * GPMC settings - 263 * Definitions is as per the following format 264 * #define <PART>_GPMC_CONFIG<x> <value> 265 * Where: 266 * PART is the part name e.g. STNOR - Intel Strata Flash 267 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 268 * Value is corresponding value 269 * 270 * For every valid PRCM configuration there should be only one definition of 271 * the same. if values are independent of the board, this definition will be 272 * present in this file if values are dependent on the board, then this should 273 * go into corresponding mem-boardName.h file 274 * 275 * Currently valid part Names are (PART): 276 * STNOR - Intel Strata Flash 277 * SMNAND - Samsung NAND 278 * MPDB - H4 MPDB board 279 * SBNOR - Sibley NOR 280 * MNAND - Micron Large page x16 NAND 281 * ONNAND - Samsung One NAND 282 * 283 * include/configs/file.h contains the defn - for all CS we are interested 284 * #define OMAP34XX_GPMC_CSx PART 285 * #define OMAP34XX_GPMC_CSx_SIZE Size 286 * #define OMAP34XX_GPMC_CSx_MAP Map 287 * Where: 288 * x - CS number 289 * PART - Part Name as defined above 290 * SIZE - how big is the mapping to be 291 * GPMC_SIZE_128M - 0x8 292 * GPMC_SIZE_64M - 0xC 293 * GPMC_SIZE_32M - 0xE 294 * GPMC_SIZE_16M - 0xF 295 * MAP - Map this CS to which address(GPMC address space)- Absolute address 296 * >>24 before being used. 297 */ 298 #define GPMC_SIZE_128M 0x8 299 #define GPMC_SIZE_64M 0xC 300 #define GPMC_SIZE_32M 0xE 301 #define GPMC_SIZE_16M 0xF 302 303 #define SMNAND_GPMC_CONFIG1 0x00000800 304 #define SMNAND_GPMC_CONFIG2 0x00141400 305 #define SMNAND_GPMC_CONFIG3 0x00141400 306 #define SMNAND_GPMC_CONFIG4 0x0F010F01 307 #define SMNAND_GPMC_CONFIG5 0x010C1414 308 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 309 #define SMNAND_GPMC_CONFIG7 0x00000C44 310 311 #define M_NAND_GPMC_CONFIG1 0x00001800 312 #define M_NAND_GPMC_CONFIG2 0x00141400 313 #define M_NAND_GPMC_CONFIG3 0x00141400 314 #define M_NAND_GPMC_CONFIG4 0x0F010F01 315 #define M_NAND_GPMC_CONFIG5 0x010C1414 316 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 317 #define M_NAND_GPMC_CONFIG7 0x00000C44 318 319 #define STNOR_GPMC_CONFIG1 0x3 320 #define STNOR_GPMC_CONFIG2 0x00151501 321 #define STNOR_GPMC_CONFIG3 0x00060602 322 #define STNOR_GPMC_CONFIG4 0x11091109 323 #define STNOR_GPMC_CONFIG5 0x01141F1F 324 #define STNOR_GPMC_CONFIG6 0x000004c4 325 326 #define SIBNOR_GPMC_CONFIG1 0x1200 327 #define SIBNOR_GPMC_CONFIG2 0x001f1f00 328 #define SIBNOR_GPMC_CONFIG3 0x00080802 329 #define SIBNOR_GPMC_CONFIG4 0x1C091C09 330 #define SIBNOR_GPMC_CONFIG5 0x01131F1F 331 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 332 333 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 334 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 335 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 336 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 337 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 338 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 339 340 #define MPDB_GPMC_CONFIG1 0x00011000 341 #define MPDB_GPMC_CONFIG2 0x001f1f01 342 #define MPDB_GPMC_CONFIG3 0x00080803 343 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 344 #define MPDB_GPMC_CONFIG5 0x041f1F1F 345 #define MPDB_GPMC_CONFIG6 0x1F0F04C4 346 347 #define P2_GPMC_CONFIG1 0x0 348 #define P2_GPMC_CONFIG2 0x0 349 #define P2_GPMC_CONFIG3 0x0 350 #define P2_GPMC_CONFIG4 0x0 351 #define P2_GPMC_CONFIG5 0x0 352 #define P2_GPMC_CONFIG6 0x0 353 354 #define ONENAND_GPMC_CONFIG1 0x00001200 355 #define ONENAND_GPMC_CONFIG2 0x000F0F01 356 #define ONENAND_GPMC_CONFIG3 0x00030301 357 #define ONENAND_GPMC_CONFIG4 0x0F040F04 358 #define ONENAND_GPMC_CONFIG5 0x010F1010 359 #define ONENAND_GPMC_CONFIG6 0x1F060000 360 361 #define NET_GPMC_CONFIG1 0x00001000 362 #define NET_GPMC_CONFIG2 0x001e1e01 363 #define NET_GPMC_CONFIG3 0x00080300 364 #define NET_GPMC_CONFIG4 0x1c091c09 365 #define NET_GPMC_CONFIG5 0x04181f1f 366 #define NET_GPMC_CONFIG6 0x00000FCF 367 #define NET_GPMC_CONFIG7 0x00000f6c 368 369 /* max number of GPMC Chip Selects */ 370 #define GPMC_MAX_CS 8 371 /* max number of GPMC regs */ 372 #define GPMC_MAX_REG 7 373 374 #define PISMO1_NOR 1 375 #define PISMO1_NAND 2 376 #define PISMO2_CS0 3 377 #define PISMO2_CS1 4 378 #define PISMO1_ONENAND 5 379 #define DBG_MPDB 6 380 #define PISMO2_NAND_CS0 7 381 #define PISMO2_NAND_CS1 8 382 383 /* make it readable for the gpmc_init */ 384 #define PISMO1_NOR_BASE FLASH_BASE 385 #define PISMO1_NAND_BASE NAND_BASE 386 #define PISMO2_CS0_BASE PISMO2_MAP1 387 #define PISMO1_ONEN_BASE ONENAND_MAP 388 #define DBG_MPDB_BASE DEBUG_BASE 389 390 #ifndef __ASSEMBLY__ 391 392 /* Function prototypes */ 393 void mem_init(void); 394 395 u32 is_mem_sdr(void); 396 u32 mem_ok(u32 cs); 397 398 u32 get_sdr_cs_size(u32); 399 u32 get_sdr_cs_offset(u32); 400 401 #endif /* __ASSEMBLY__ */ 402 403 #endif /* endif _MEM_H_ */ 404