1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _MEM_H_ 26 #define _MEM_H_ 27 28 #define CS0 0x0 29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31 #ifndef __ASSEMBLY__ 32 enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37 }; 38 #endif /* __ASSEMBLY__ */ 39 40 #define EARLY_INIT 1 41 42 /* 43 * For a full explanation of these registers and values please see 44 * the Technical Reference Manual (TRM) for any of the processors in 45 * this family. 46 */ 47 48 /* Slower full frequency range default timings for x32 operation*/ 49 #define SDRC_SHARING 0x00000100 50 #define SDRC_MR_0_SDR 0x00000031 51 52 #define DLL_OFFSET 0 53 #define DLL_WRITEDDRCLKX2DIS 1 54 #define DLL_ENADLL 1 55 #define DLL_LOCKDLL 0 56 #define DLL_DLLPHASE_72 0 57 #define DLL_DLLPHASE_90 1 58 59 /* rkw - need to find of 90/72 degree recommendation for speed like before */ 60 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 61 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 62 63 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 64 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 65 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 66 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 67 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 68 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 69 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 70 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 71 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 72 73 #define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \ 74 ACTIM_CTRLA_TRFC(a) | \ 75 ACTIM_CTRLA_TRC(b) | \ 76 ACTIM_CTRLA_TRAS(b) | \ 77 ACTIM_CTRLA_TRP(d) | \ 78 ACTIM_CTRLA_TRCD(e) | \ 79 ACTIM_CTRLA_TRRD(f) | \ 80 ACTIM_CTRLA_TDPL(g) | \ 81 ACTIM_CTRLA_TDAL(h) 82 83 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 84 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 85 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 86 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 87 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 88 89 #define ACTIM_CTRLB(a,b,c,d) \ 90 ACTIM_CTRLB_TWTR(a) | \ 91 ACTIM_CTRLB_TCKE(b) | \ 92 ACTIM_CTRLB_TXP(b) | \ 93 ACTIM_CTRLB_TXSR(d) 94 95 /* 96 * Values used in the MCFG register. Only values we use today 97 * are defined and the rest can be found in the TRM. Unless otherwise 98 * noted all fields are one bit. 99 */ 100 #define V_MCFG_RAMTYPE_DDR (0x1) 101 #define V_MCFG_DEEPPD_EN (0x1 << 3) 102 #define V_MCFG_B32NOT16_32 (0x1 << 4) 103 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ 104 #define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ 105 #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) 106 #define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ 107 #define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ 108 109 /* Macro to construct MCFG */ 110 #define MCFG(a, b) \ 111 V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ 112 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ 113 V_MCFG_BANKALLOCATION_RBC | \ 114 V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR 115 116 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ 117 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 118 /* 15/6 + 18/6 = 5.5 -> 6 */ 119 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 120 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */ 121 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */ 122 #define INFINEON_TRP_165 3 /* 18/6 = 3 */ 123 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */ 124 #define INFINEON_TRC_165 10 /* 60/6 = 10 */ 125 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */ 126 127 #define INFINEON_V_ACTIMA_165 \ 128 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 129 INFINEON_TRAS_165, INFINEON_TRP_165, \ 130 INFINEON_TRCD_165, INFINEON_TRRD_165, \ 131 INFINEON_TDPL_165, INFINEON_TDAL_165) 132 133 #define INFINEON_TWTR_165 1 134 #define INFINEON_TCKE_165 2 135 #define INFINEON_TXP_165 2 136 #define INFINEON_XSR_165 20 /* 120/6 = 20 */ 137 138 #define INFINEON_V_ACTIMB_165 \ 139 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 140 INFINEON_TXP_165, INFINEON_XSR_165) 141 142 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ 143 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 144 /* 15/6 + 18/6 = 5.5 -> 6 */ 145 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 146 #define MICRON_TRRD_165 2 /* 12/6 = 2 */ 147 #define MICRON_TRCD_165 3 /* 18/6 = 3 */ 148 #define MICRON_TRP_165 3 /* 18/6 = 3 */ 149 #define MICRON_TRAS_165 7 /* 42/6 = 7 */ 150 #define MICRON_TRC_165 10 /* 60/6 = 10 */ 151 #define MICRON_TRFC_165 21 /* 125/6 = 21 */ 152 153 #define MICRON_V_ACTIMA_165 \ 154 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 155 MICRON_TRAS_165, MICRON_TRP_165, \ 156 MICRON_TRCD_165, MICRON_TRRD_165, \ 157 MICRON_TDPL_165, MICRON_TDAL_165) 158 159 #define MICRON_TWTR_165 1 160 #define MICRON_TCKE_165 1 161 #define MICRON_XSR_165 23 /* 138/6 = 23 */ 162 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ 163 164 #define MICRON_V_ACTIMB_165 \ 165 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 166 MICRON_TXP_165, MICRON_XSR_165) 167 168 #define MICRON_RASWIDTH 0x2 169 #define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) 170 171 #define MICRON_ARCV 2030 172 #define MICRON_ARE 0x1 173 #define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) 174 175 #define MICRON_BL 0x2 176 #define MICRON_SIL 0x0 177 #define MICRON_CASL 0x3 178 #define MICRON_WBST 0x0 179 #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ 180 (MICRON_SIL << 3) | (MICRON_BL)) 181 182 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ 183 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ 184 /* 15/6 + 18/6 = 5.5 -> 6 */ 185 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 186 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ 187 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ 188 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */ 189 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ 190 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */ 191 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ 192 193 #define NUMONYX_V_ACTIMA_165 \ 194 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 195 NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 196 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 197 NUMONYX_TDPL_165, NUMONYX_TDAL_165) 198 199 #define NUMONYX_TWTR_165 2 200 #define NUMONYX_TCKE_165 2 201 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ 202 #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ 203 204 #define NUMONYX_V_ACTIMB_165 \ 205 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 206 NUMONYX_TXP_165, NUMONYX_XSR_165) 207 208 #ifdef CONFIG_OMAP3_INFINEON_DDR 209 #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 210 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165 211 #endif 212 213 #ifdef CONFIG_OMAP3_MICRON_DDR 214 #define V_ACTIMA_165 MICRON_V_ACTIMA_165 215 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 216 #define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) 217 #define V_RFR_CTRL MICRON_V_RFR_CTRL 218 #define V_MR MICRON_V_MR 219 #endif 220 221 #ifdef CONFIG_OMAP3_NUMONYX_DDR 222 #define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 223 #define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 224 #endif 225 226 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 227 #error "Please choose the right DDR type in config header" 228 #endif 229 230 #if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) 231 #error "Please choose the right DDR type in config header" 232 #endif 233 234 /* 235 * GPMC settings - 236 * Definitions is as per the following format 237 * #define <PART>_GPMC_CONFIG<x> <value> 238 * Where: 239 * PART is the part name e.g. STNOR - Intel Strata Flash 240 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 241 * Value is corresponding value 242 * 243 * For every valid PRCM configuration there should be only one definition of 244 * the same. if values are independent of the board, this definition will be 245 * present in this file if values are dependent on the board, then this should 246 * go into corresponding mem-boardName.h file 247 * 248 * Currently valid part Names are (PART): 249 * STNOR - Intel Strata Flash 250 * SMNAND - Samsung NAND 251 * MPDB - H4 MPDB board 252 * SBNOR - Sibley NOR 253 * MNAND - Micron Large page x16 NAND 254 * ONNAND - Samsung One NAND 255 * 256 * include/configs/file.h contains the defn - for all CS we are interested 257 * #define OMAP34XX_GPMC_CSx PART 258 * #define OMAP34XX_GPMC_CSx_SIZE Size 259 * #define OMAP34XX_GPMC_CSx_MAP Map 260 * Where: 261 * x - CS number 262 * PART - Part Name as defined above 263 * SIZE - how big is the mapping to be 264 * GPMC_SIZE_128M - 0x8 265 * GPMC_SIZE_64M - 0xC 266 * GPMC_SIZE_32M - 0xE 267 * GPMC_SIZE_16M - 0xF 268 * MAP - Map this CS to which address(GPMC address space)- Absolute address 269 * >>24 before being used. 270 */ 271 #define GPMC_SIZE_128M 0x8 272 #define GPMC_SIZE_64M 0xC 273 #define GPMC_SIZE_32M 0xE 274 #define GPMC_SIZE_16M 0xF 275 276 #define GPMC_BASEADDR_MASK 0x3F 277 278 #define GPMC_CS_ENABLE 0x1 279 280 #define SMNAND_GPMC_CONFIG1 0x00000800 281 #define SMNAND_GPMC_CONFIG2 0x00141400 282 #define SMNAND_GPMC_CONFIG3 0x00141400 283 #define SMNAND_GPMC_CONFIG4 0x0F010F01 284 #define SMNAND_GPMC_CONFIG5 0x010C1414 285 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 286 #define SMNAND_GPMC_CONFIG7 0x00000C44 287 288 #define M_NAND_GPMC_CONFIG1 0x00001800 289 #define M_NAND_GPMC_CONFIG2 0x00141400 290 #define M_NAND_GPMC_CONFIG3 0x00141400 291 #define M_NAND_GPMC_CONFIG4 0x0F010F01 292 #define M_NAND_GPMC_CONFIG5 0x010C1414 293 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 294 #define M_NAND_GPMC_CONFIG7 0x00000C44 295 296 #define STNOR_GPMC_CONFIG1 0x3 297 #define STNOR_GPMC_CONFIG2 0x00151501 298 #define STNOR_GPMC_CONFIG3 0x00060602 299 #define STNOR_GPMC_CONFIG4 0x11091109 300 #define STNOR_GPMC_CONFIG5 0x01141F1F 301 #define STNOR_GPMC_CONFIG6 0x000004c4 302 303 #define SIBNOR_GPMC_CONFIG1 0x1200 304 #define SIBNOR_GPMC_CONFIG2 0x001f1f00 305 #define SIBNOR_GPMC_CONFIG3 0x00080802 306 #define SIBNOR_GPMC_CONFIG4 0x1C091C09 307 #define SIBNOR_GPMC_CONFIG5 0x01131F1F 308 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 309 310 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 311 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 312 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 313 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 314 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 315 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 316 317 #define MPDB_GPMC_CONFIG1 0x00011000 318 #define MPDB_GPMC_CONFIG2 0x001f1f01 319 #define MPDB_GPMC_CONFIG3 0x00080803 320 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 321 #define MPDB_GPMC_CONFIG5 0x041f1F1F 322 #define MPDB_GPMC_CONFIG6 0x1F0F04C4 323 324 #define P2_GPMC_CONFIG1 0x0 325 #define P2_GPMC_CONFIG2 0x0 326 #define P2_GPMC_CONFIG3 0x0 327 #define P2_GPMC_CONFIG4 0x0 328 #define P2_GPMC_CONFIG5 0x0 329 #define P2_GPMC_CONFIG6 0x0 330 331 #define ONENAND_GPMC_CONFIG1 0x00001200 332 #define ONENAND_GPMC_CONFIG2 0x000F0F01 333 #define ONENAND_GPMC_CONFIG3 0x00030301 334 #define ONENAND_GPMC_CONFIG4 0x0F040F04 335 #define ONENAND_GPMC_CONFIG5 0x010F1010 336 #define ONENAND_GPMC_CONFIG6 0x1F060000 337 338 #define NET_GPMC_CONFIG1 0x00001000 339 #define NET_GPMC_CONFIG2 0x001e1e01 340 #define NET_GPMC_CONFIG3 0x00080300 341 #define NET_GPMC_CONFIG4 0x1c091c09 342 #define NET_GPMC_CONFIG5 0x04181f1f 343 #define NET_GPMC_CONFIG6 0x00000FCF 344 #define NET_GPMC_CONFIG7 0x00000f6c 345 346 /* max number of GPMC Chip Selects */ 347 #define GPMC_MAX_CS 8 348 /* max number of GPMC regs */ 349 #define GPMC_MAX_REG 7 350 351 #define PISMO1_NOR 1 352 #define PISMO1_NAND 2 353 #define PISMO2_CS0 3 354 #define PISMO2_CS1 4 355 #define PISMO1_ONENAND 5 356 #define DBG_MPDB 6 357 #define PISMO2_NAND_CS0 7 358 #define PISMO2_NAND_CS1 8 359 360 /* make it readable for the gpmc_init */ 361 #define PISMO1_NOR_BASE FLASH_BASE 362 #define PISMO1_NAND_BASE NAND_BASE 363 #define PISMO2_CS0_BASE PISMO2_MAP1 364 #define PISMO1_ONEN_BASE ONENAND_MAP 365 #define DBG_MPDB_BASE DEBUG_BASE 366 367 #ifndef __ASSEMBLY__ 368 369 /* Function prototypes */ 370 void mem_init(void); 371 372 u32 is_mem_sdr(void); 373 u32 mem_ok(u32 cs); 374 375 u32 get_sdr_cs_size(u32); 376 u32 get_sdr_cs_offset(u32); 377 378 #endif /* __ASSEMBLY__ */ 379 380 #endif /* endif _MEM_H_ */ 381