1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_MX7_IMX_REGS_H__ 8 #define __ASM_ARCH_MX7_IMX_REGS_H__ 9 10 #define ARCH_MXC 11 12 #define CONFIG_SYS_CACHELINE_SIZE 64 13 14 #define ROM_SW_INFO_ADDR 0x000001E8 15 #define ROMCP_ARB_BASE_ADDR 0x00000000 16 #define ROMCP_ARB_END_ADDR 0x00017FFF 17 #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR 18 #define CAAM_ARB_BASE_ADDR 0x00100000 19 #define CAAM_ARB_END_ADDR 0x00107FFF 20 #define GIC400_ARB_BASE_ADDR 0x31000000 21 #define GIC400_ARB_END_ADDR 0x31007FFF 22 #define APBH_DMA_ARB_BASE_ADDR 0x33000000 23 #define APBH_DMA_ARB_END_ADDR 0x33007FFF 24 #define M4_BOOTROM_BASE_ADDR 0x00180000 25 26 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 27 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 28 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 29 30 /* GPV - PL301 configuration ports */ 31 #define GPV0_BASE_ADDR 0x32000000 32 #define GPV1_BASE_ADDR 0x32100000 33 #define GPV2_BASE_ADDR 0x32200000 34 #define GPV3_BASE_ADDR 0x32300000 35 #define GPV4_BASE_ADDR 0x32400000 36 #define GPV5_BASE_ADDR 0x32500000 37 #define GPV6_BASE_ADDR 0x32600000 38 #define GPV7_BASE_ADDR 0x32700000 39 40 #define OCRAM_ARB_BASE_ADDR 0x00900000 41 #define OCRAM_ARB_END_ADDR 0x0091FFFF 42 #define OCRAM_EPDC_BASE_ADDR 0x00920000 43 #define OCRAM_EPDC_END_ADDR 0x0093FFFF 44 #define OCRAM_PXP_BASE_ADDR 0x00940000 45 #define OCRAM_PXP_END_ADDR 0x00947FFF 46 #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR 47 #define IRAM_SIZE 0x00020000 48 49 #define AIPS1_ARB_BASE_ADDR 0x30000000 50 #define AIPS1_ARB_END_ADDR 0x303FFFFF 51 #define AIPS2_ARB_BASE_ADDR 0x30400000 52 #define AIPS2_ARB_END_ADDR 0x307FFFFF 53 #define AIPS3_ARB_BASE_ADDR 0x30800000 54 #define AIPS3_ARB_END_ADDR 0x30BFFFFF 55 56 #define WEIM_ARB_BASE_ADDR 0x28000000 57 #define WEIM_ARB_END_ADDR 0x2FFFFFFF 58 59 #define QSPI0_ARB_BASE_ADDR 0x60000000 60 #define QSPI0_ARB_END_ADDR 0x6FFFFFFF 61 #define PCIE_ARB_BASE_ADDR 0x40000000 62 #define PCIE_ARB_END_ADDR 0x4FFFFFFF 63 #define PCIE_REG_BASE_ADDR 0x33800000 64 #define PCIE_REG_END_ADDR 0x33803FFF 65 66 #define MMDC0_ARB_BASE_ADDR 0x80000000 67 #define MMDC0_ARB_END_ADDR 0xBFFFFFFF 68 #define MMDC1_ARB_BASE_ADDR 0xC0000000 69 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 70 71 /* Cortex-A9 MPCore private memory region */ 72 #define ARM_PERIPHBASE 0x31000000 73 #define SCU_BASE_ADDR ARM_PERIPHBASE 74 #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) 75 #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) 76 77 78 /* Defines for Blocks connected via AIPS (SkyBlue) */ 79 #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 80 #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 81 #define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 82 83 /* DAP base-address */ 84 #define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR 85 86 /* AIPS_TZ#1- On Platform */ 87 #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) 88 /* AIPS_TZ#1- Off Platform */ 89 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) 90 91 #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR 92 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) 93 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) 94 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) 95 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) 96 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) 97 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) 98 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) 99 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) 100 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) 101 #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) 102 #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) 103 #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) 104 #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) 105 #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR 106 #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) 107 #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) 108 #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) 109 #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) 110 #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) 111 #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) 112 #define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR 113 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) 114 #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) 115 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) 116 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) 117 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) 118 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) 119 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) 120 #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) 121 #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) 122 #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) 123 #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) 124 125 /* AIPS_TZ#2- On Platform */ 126 #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) 127 /* AIPS_TZ#2- Off Platform */ 128 #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) 129 #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) 130 #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) 131 #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) 132 #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) 133 #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) 134 #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) 135 #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) 136 #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) 137 #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) 138 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) 139 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) 140 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) 141 #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) 142 #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) 143 #define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR 144 #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) 145 #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) 146 #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) 147 #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) 148 #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) 149 #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) 150 #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) 151 #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) 152 #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) 153 #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) 154 #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) 155 #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) 156 157 /* AIPS_TZ#3 - Global enable (0) */ 158 #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) 159 #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) 160 #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) 161 #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) 162 #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) 163 #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) 164 #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) 165 #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) 166 #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) 167 #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) 168 #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) 169 170 /* AIPS_TZ#3- On Platform */ 171 #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) 172 /* AIPS_TZ#3- Off Platform */ 173 #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) 174 #define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR 175 #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) 176 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) 177 #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) 178 #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) 179 #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) 180 #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) 181 #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) 182 #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) 183 #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) 184 #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) 185 #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) 186 #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) 187 #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) 188 #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) 189 #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) 190 #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) 191 #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) 192 #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) 193 #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) 194 #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) 195 #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) 196 #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) 197 #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) 198 #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) 199 #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) 200 #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) 201 #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) 202 #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) 203 204 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 205 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 206 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 207 208 #define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR 209 #define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR 210 211 #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR 212 #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR 213 214 #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR 215 216 #define FEC_QUIRK_ENET_MAC 217 #define SNVS_LPGPR 0x68 218 219 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR) 220 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + 0x1000) 221 222 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 223 #include <asm/imx-common/regs-lcdif.h> 224 #include <asm/types.h> 225 226 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 227 228 /* System Reset Controller (SRC) */ 229 struct src { 230 u32 scr; 231 u32 a7rcr0; 232 u32 a7rcr1; 233 u32 m4rcr; 234 u32 reserved1; 235 u32 ercr; 236 u32 reserved2; 237 u32 hsicphy_rcr; 238 u32 usbophy1_rcr; 239 u32 usbophy2_rcr; 240 u32 mipiphy_rcr; 241 u32 pciephy_rcr; 242 u32 reserved3[10]; 243 u32 sbmr1; 244 u32 srsr; 245 u32 reserved4[2]; 246 u32 sisr; 247 u32 simr; 248 u32 sbmr2; 249 u32 gpr1; 250 u32 gpr2; 251 u32 gpr3; 252 u32 gpr4; 253 u32 gpr5; 254 u32 gpr6; 255 u32 gpr7; 256 u32 gpr8; 257 u32 gpr9; 258 u32 gpr10; 259 u32 reserved5[985]; 260 u32 ddrc_rcr; 261 }; 262 263 /* GPR0 Bit Fields */ 264 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u 265 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 266 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u 267 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 268 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u 269 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 270 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u 271 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 272 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u 273 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 274 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u 275 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 276 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u 277 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 278 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) 279 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 280 /* GPR1 Bit Fields */ 281 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u 282 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 283 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u 284 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 285 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) 286 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u 287 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 288 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u 289 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 290 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) 291 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u 292 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 293 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u 294 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 295 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) 296 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u 297 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 298 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u 299 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 300 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) 301 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u 302 #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 303 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u 304 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 305 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u 306 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 307 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u 308 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 309 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u 310 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 311 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u 312 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 313 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u 314 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 315 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u 316 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 317 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u 318 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 319 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u 320 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 321 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) 322 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u 323 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 324 /* GPR2 Bit Fields */ 325 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u 326 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 327 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u 328 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 329 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u 330 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 331 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u 332 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 333 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u 334 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 335 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u 336 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 337 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u 338 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 339 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u 340 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 341 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u 342 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 343 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u 344 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 345 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u 346 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 347 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u 348 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 349 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u 350 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 351 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u 352 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 353 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u 354 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 355 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u 356 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 357 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u 358 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 359 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) 360 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u 361 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 362 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u 363 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 364 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u 365 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 366 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u 367 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 368 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u 369 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 370 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u 371 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 372 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u 373 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 374 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u 375 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 376 /* GPR3 Bit Fields */ 377 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u 378 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 379 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u 380 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 381 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u 382 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 383 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u 384 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 385 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u 386 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 387 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u 388 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 389 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u 390 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 391 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u 392 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 393 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u 394 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 395 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u 396 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 397 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u 398 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 399 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u 400 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 401 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u 402 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 403 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u 404 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 405 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u 406 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 407 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u 408 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 409 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u 410 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 411 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u 412 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 413 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u 414 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 415 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u 416 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 417 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u 418 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 419 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u 420 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 421 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u 422 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 423 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u 424 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 425 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u 426 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 427 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u 428 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 429 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u 430 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 431 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u 432 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 433 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u 434 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 435 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u 436 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 437 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u 438 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 439 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u 440 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 441 /* GPR4 Bit Fields */ 442 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u 443 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 444 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u 445 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 446 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u 447 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 448 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u 449 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 450 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u 451 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 452 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u 453 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 454 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u 455 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 456 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u 457 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 458 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u 459 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 460 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u 461 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 462 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u 463 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 464 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u 465 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 466 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u 467 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 468 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u 469 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 470 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u 471 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 472 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u 473 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 474 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u 475 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 476 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) 477 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u 478 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 479 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) 480 /* GPR5 Bit Fields */ 481 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u 482 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 483 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u 484 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 485 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u 486 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 487 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u 488 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 489 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u 490 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 491 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u 492 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 493 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u 494 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 495 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u 496 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 497 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u 498 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 499 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u 500 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 501 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u 502 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 503 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u 504 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 505 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u 506 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 507 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u 508 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 509 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u 510 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 511 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u 512 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 513 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u 514 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 515 /* GPR6 Bit Fields */ 516 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u 517 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 518 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u 519 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 520 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u 521 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 522 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u 523 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 524 /* GPR7 Bit Fields */ 525 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u 526 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 527 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u 528 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 529 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u 530 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 531 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u 532 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 533 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u 534 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 535 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) 536 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u 537 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 538 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u 539 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 540 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u 541 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 542 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u 543 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 544 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u 545 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 546 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) 547 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u 548 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 549 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u 550 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 551 /* GPR8 Bit Fields */ 552 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u 553 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 554 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) 555 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u 556 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 557 /* GPR9 Bit Fields */ 558 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u 559 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 560 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu 561 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 562 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) 563 /* GPR10 Bit Fields */ 564 #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u 565 #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 566 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u 567 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 568 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u 569 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 570 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u 571 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 572 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u 573 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 574 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) 575 /* GPR11 Bit Fields */ 576 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u 577 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 578 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu 579 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 580 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) 581 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u 582 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 583 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u 584 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 585 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) 586 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u 587 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 588 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u 589 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 590 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) 591 /* GPR12 Bit Fields */ 592 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u 593 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 594 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u 595 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 596 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u 597 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 598 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u 599 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 600 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u 601 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 602 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u 603 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 604 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) 605 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u 606 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 607 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) 608 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u 609 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 610 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) 611 /* GPR13 Bit Fields */ 612 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u 613 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 614 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u 615 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 616 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u 617 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 618 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u 619 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 620 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u 621 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 622 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u 623 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 624 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u 625 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 626 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u 627 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 628 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u 629 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 630 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u 631 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 632 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u 633 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 634 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u 635 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 636 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u 637 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 638 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u 639 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 640 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u 641 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 642 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u 643 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 644 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u 645 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 646 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) 647 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u 648 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 649 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) 650 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u 651 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 652 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u 653 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 654 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u 655 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 656 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u 657 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 658 /* GPR14 Bit Fields */ 659 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u 660 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 661 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u 662 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 663 /* GPR15 Bit Fields */ 664 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u 665 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 666 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u 667 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 668 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu 669 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 670 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) 671 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u 672 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 673 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) 674 /* GPR16 Bit Fields */ 675 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u 676 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 677 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) 678 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u 679 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 680 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u 681 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 682 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u 683 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 684 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u 685 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 686 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u 687 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 688 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) 689 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u 690 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 691 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u 692 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 693 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u 694 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 695 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u 696 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 697 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) 698 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u 699 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 700 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u 701 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 702 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u 703 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 704 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) 705 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u 706 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 707 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u 708 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 709 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u 710 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 711 /* GPR17 Bit Fields */ 712 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu 713 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 714 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) 715 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u 716 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 717 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) 718 /* GPR18 Bit Fields */ 719 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u 720 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 721 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) 722 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u 723 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 724 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) 725 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u 726 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 727 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) 728 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u 729 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 730 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) 731 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u 732 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 733 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u 734 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 735 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) 736 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u 737 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 738 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) 739 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u 740 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 741 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u 742 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 743 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u 744 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 745 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u 746 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 747 /* GPR19 Bit Fields */ 748 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u 749 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 750 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u 751 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 752 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) 753 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u 754 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 755 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u 756 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 757 /* GPR20 Bit Fields */ 758 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu 759 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 760 #define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) 761 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u 762 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 763 #define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) 764 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u 765 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 766 #define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) 767 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u 768 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 769 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u 770 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 771 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u 772 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 773 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) 774 /* GPR21 Bit Fields */ 775 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u 776 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 777 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) 778 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u 779 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 780 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) 781 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u 782 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 783 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) 784 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u 785 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 786 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) 787 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u 788 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 789 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) 790 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u 791 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 792 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) 793 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u 794 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 795 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u 796 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 797 /* GPR22 Bit Fields */ 798 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u 799 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 800 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) 801 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u 802 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 803 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u 804 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 805 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u 806 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 807 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u 808 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 809 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u 810 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 811 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u 812 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 813 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u 814 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 815 816 #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4) 817 #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4) 818 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4) 819 820 struct iomuxc { 821 u32 gpr[23]; 822 /* mux and pad registers */ 823 }; 824 825 struct iomuxc_gpr_base_regs { 826 u32 gpr[23]; /* 0x000 */ 827 }; 828 829 /* ECSPI registers */ 830 struct cspi_regs { 831 u32 rxdata; 832 u32 txdata; 833 u32 ctrl; 834 u32 cfg; 835 u32 intr; 836 u32 dma; 837 u32 stat; 838 u32 period; 839 }; 840 841 /* 842 * CSPI register definitions 843 */ 844 #define MXC_ECSPI 845 #define MXC_CSPICTRL_EN (1 << 0) 846 #define MXC_CSPICTRL_MODE (1 << 1) 847 #define MXC_CSPICTRL_XCH (1 << 2) 848 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 849 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 850 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 851 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 852 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 853 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 854 #define MXC_CSPICTRL_MAXBITS 0xfff 855 #define MXC_CSPICTRL_TC (1 << 7) 856 #define MXC_CSPICTRL_RXOVF (1 << 6) 857 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 858 #define MAX_SPI_BYTES 32 859 860 /* Bit position inside CTRL register to be associated with SS */ 861 #define MXC_CSPICTRL_CHAN 18 862 863 /* Bit position inside CON register to be associated with SS */ 864 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 865 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 866 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 867 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 868 869 #define MXC_SPI_BASE_ADDRESSES \ 870 ECSPI1_BASE_ADDR, \ 871 ECSPI2_BASE_ADDR, \ 872 ECSPI3_BASE_ADDR, \ 873 ECSPI4_BASE_ADDR 874 875 #define CSU_INIT_SEC_LEVEL0 0x00FF00FF 876 #define CSU_NUM_REGS 64 877 878 struct ocotp_regs { 879 u32 ctrl; 880 u32 ctrl_set; 881 u32 ctrl_clr; 882 u32 ctrl_tog; 883 u32 timing; 884 u32 rsvd0[3]; 885 u32 data0; 886 u32 rsvd1[3]; 887 u32 data1; 888 u32 rsvd2[3]; 889 u32 data2; 890 u32 rsvd3[3]; 891 u32 data3; 892 u32 rsvd4[3]; 893 u32 read_ctrl; 894 u32 rsvd5[3]; 895 u32 read_fuse_data0; 896 u32 rsvd6[3]; 897 u32 read_fuse_data1; 898 u32 rsvd7[3]; 899 u32 read_fuse_data2; 900 u32 rsvd8[3]; 901 u32 read_fuse_data3; 902 u32 rsvd9[3]; 903 u32 sw_sticky; 904 u32 rsvd10[3]; 905 u32 scs; 906 u32 scs_set; 907 u32 scs_clr; 908 u32 scs_tog; 909 u32 crc_addr; 910 u32 rsvd11[3]; 911 u32 crc_value; 912 u32 rsvd12[3]; 913 u32 version; 914 u32 rsvd13[0xc3]; 915 916 struct fuse_bank { /* offset 0x400 */ 917 u32 fuse_regs[0x10]; 918 } bank[16]; 919 }; 920 921 struct fuse_bank0_regs { 922 u32 lock; 923 u32 rsvd0[3]; 924 u32 tester0; 925 u32 rsvd1[3]; 926 u32 tester1; 927 u32 rsvd2[3]; 928 u32 tester2; 929 u32 rsvd3[3]; 930 }; 931 932 struct fuse_bank1_regs { 933 u32 tester3; 934 u32 rsvd0[3]; 935 u32 tester4; 936 u32 rsvd1[3]; 937 u32 tester5; 938 u32 rsvd2[3]; 939 u32 cfg0; 940 u32 rsvd3[3]; 941 }; 942 943 struct fuse_bank2_regs { 944 u32 cfg1; 945 u32 rsvd0[3]; 946 u32 cfg2; 947 u32 rsvd1[3]; 948 u32 cfg3; 949 u32 rsvd2[3]; 950 u32 cfg4; 951 u32 rsvd3[3]; 952 }; 953 954 struct fuse_bank3_regs { 955 u32 mem_trim0; 956 u32 rsvd0[3]; 957 u32 mem_trim1; 958 u32 rsvd1[3]; 959 u32 ana0; 960 u32 rsvd2[3]; 961 u32 ana1; 962 u32 rsvd3[3]; 963 }; 964 965 struct fuse_bank8_regs { 966 u32 sjc_resp_low; 967 u32 rsvd0[3]; 968 u32 sjc_resp_high; 969 u32 rsvd1[3]; 970 u32 usb_id; 971 u32 rsvd2[3]; 972 u32 field_return; 973 u32 rsvd3[3]; 974 }; 975 976 struct fuse_bank9_regs { 977 u32 mac_addr0; 978 u32 rsvd0[3]; 979 u32 mac_addr1; 980 u32 rsvd1[3]; 981 u32 mac_addr2; 982 u32 rsvd2[7]; 983 }; 984 985 struct aipstz_regs { 986 u32 mprot0; 987 u32 mprot1; 988 u32 rsvd[0xe]; 989 u32 opacr0; 990 u32 opacr1; 991 u32 opacr2; 992 u32 opacr3; 993 u32 opacr4; 994 }; 995 996 struct wdog_regs { 997 u16 wcr; /* Control */ 998 u16 wsr; /* Service */ 999 u16 wrsr; /* Reset Status */ 1000 u16 wicr; /* Interrupt Control */ 1001 u16 wmcr; /* Miscellaneous Control */ 1002 }; 1003 1004 struct dbg_monitor_regs { 1005 u32 ctrl[4]; /* Control */ 1006 u32 master_en[4]; /* Master enable */ 1007 u32 irq[4]; /* IRQ */ 1008 u32 trap_addr_low[4]; /* Trap address low */ 1009 u32 trap_addr_high[4]; /* Trap address high */ 1010 u32 trap_id[4]; /* Trap ID */ 1011 u32 snvs_addr[4]; /* SNVS address */ 1012 u32 snvs_data[4]; /* SNVS data */ 1013 u32 snvs_info[4]; /* SNVS info */ 1014 u32 version[4]; /* Version */ 1015 }; 1016 1017 struct rdc_regs { 1018 u32 vir; /* Version information */ 1019 u32 reserved1[8]; 1020 u32 stat; /* Status */ 1021 u32 intctrl; /* Interrupt and Control */ 1022 u32 intstat; /* Interrupt Status */ 1023 u32 reserved2[116]; 1024 u32 mda[27]; /* Master Domain Assignment */ 1025 u32 reserved3[101]; 1026 u32 pdap[118]; /* Peripheral Domain Access Permissions */ 1027 u32 reserved4[138]; 1028 struct { 1029 u32 mrsa; /* Memory Region Start Address */ 1030 u32 mrea; /* Memory Region End Address */ 1031 u32 mrc; /* Memory Region Control */ 1032 u32 mrvs; /* Memory Region Violation Status */ 1033 } mem_region[52]; 1034 }; 1035 1036 struct rdc_sema_regs { 1037 u8 gate[64]; /* Gate */ 1038 u16 rstgt; /* Reset Gate */ 1039 }; 1040 1041 #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR 1042 1043 #define LCDIF_CTRL_SFTRST (1 << 31) 1044 #define LCDIF_CTRL_CLKGATE (1 << 30) 1045 #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) 1046 #define LCDIF_CTRL_READ_WRITEB (1 << 28) 1047 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) 1048 #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) 1049 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) 1050 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 1051 #define LCDIF_CTRL_DVI_MODE (1 << 20) 1052 #define LCDIF_CTRL_BYPASS_COUNT (1 << 19) 1053 #define LCDIF_CTRL_VSYNC_MODE (1 << 18) 1054 #define LCDIF_CTRL_DOTCLK_MODE (1 << 17) 1055 #define LCDIF_CTRL_DATA_SELECT (1 << 16) 1056 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) 1057 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 1058 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) 1059 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 1060 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) 1061 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 1062 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) 1063 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) 1064 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) 1065 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) 1066 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) 1067 #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 1068 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) 1069 #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) 1070 #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) 1071 #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) 1072 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) 1073 #define LCDIF_CTRL_LCDIF_MASTER (1 << 5) 1074 #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) 1075 #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) 1076 #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) 1077 #define LCDIF_CTRL_RUN (1 << 0) 1078 1079 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) 1080 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) 1081 #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) 1082 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) 1083 #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) 1084 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) 1085 #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) 1086 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) 1087 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) 1088 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 1089 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) 1090 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) 1091 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) 1092 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) 1093 #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) 1094 #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) 1095 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) 1096 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) 1097 #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) 1098 #define LCDIF_CTRL1_MODE86 (1 << 1) 1099 #define LCDIF_CTRL1_RESET (1 << 0) 1100 1101 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) 1102 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 1103 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) 1104 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) 1105 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) 1106 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) 1107 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) 1108 #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) 1109 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) 1110 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 1111 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) 1112 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) 1113 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) 1114 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) 1115 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) 1116 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) 1117 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) 1118 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 1119 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) 1120 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) 1121 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) 1122 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) 1123 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) 1124 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) 1125 #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) 1126 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) 1127 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) 1128 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) 1129 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 1130 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) 1131 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 1132 1133 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) 1134 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 1135 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) 1136 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 1137 1138 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff 1139 #define LCDIF_CUR_BUF_ADDR_OFFSET 0 1140 1141 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff 1142 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0 1143 1144 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) 1145 #define LCDIF_TIMING_CMD_HOLD_OFFSET 24 1146 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) 1147 #define LCDIF_TIMING_CMD_SETUP_OFFSET 16 1148 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) 1149 #define LCDIF_TIMING_DATA_HOLD_OFFSET 8 1150 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) 1151 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0 1152 1153 #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) 1154 #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) 1155 #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) 1156 #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) 1157 #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) 1158 #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) 1159 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) 1160 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) 1161 #define LCDIF_VDCTRL0_HALF_LINE (1 << 19) 1162 #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) 1163 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff 1164 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 1165 1166 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff 1167 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 1168 1169 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) 1170 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 1171 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff 1172 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 1173 1174 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) 1175 #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) 1176 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) 1177 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 1178 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) 1179 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 1180 1181 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) 1182 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 1183 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) 1184 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff 1185 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 1186 1187 1188 extern void check_cpu_temperature(void); 1189 1190 extern void pcie_power_up(void); 1191 extern void pcie_power_off(void); 1192 1193 /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB 1194 * If boot from the other mode, USB0_PWD will keep reset value 1195 */ 1196 #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ 1197 readl(USBOTG2_IPS_BASE_ADDR + 0x158)) 1198 #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) 1199 1200 /* Boot device type */ 1201 #define BOOT_TYPE_SD 0x1 1202 #define BOOT_TYPE_MMC 0x2 1203 #define BOOT_TYPE_NAND 0x3 1204 #define BOOT_TYPE_QSPI 0x4 1205 #define BOOT_TYPE_WEIM 0x5 1206 #define BOOT_TYPE_SPINOR 0x6 1207 1208 struct bootrom_sw_info { 1209 u8 reserved_1; 1210 u8 boot_dev_instance; 1211 u8 boot_dev_type; 1212 u8 reserved_2; 1213 u32 arm_core_freq; 1214 u32 axi_freq; 1215 u32 ddr_freq; 1216 u32 gpt1_freq; 1217 u32 reserved_3[3]; 1218 }; 1219 1220 #endif /* __ASSEMBLER__*/ 1221 #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ 1222