1*05d54b82SFabio Estevam /* 2*05d54b82SFabio Estevam * Copyright (C) 2014 Freescale Semiconductor, Inc. 3*05d54b82SFabio Estevam * 4*05d54b82SFabio Estevam * SPDX-License-Identifier: GPL-2.0+ 5*05d54b82SFabio Estevam */ 6*05d54b82SFabio Estevam 7*05d54b82SFabio Estevam #ifndef __ASM_ARCH_MX6SX_DDR_H__ 8*05d54b82SFabio Estevam #define __ASM_ARCH_MX6SX_DDR_H__ 9*05d54b82SFabio Estevam 10*05d54b82SFabio Estevam #ifndef CONFIG_MX6SX 11*05d54b82SFabio Estevam #error "wrong CPU" 12*05d54b82SFabio Estevam #endif 13*05d54b82SFabio Estevam 14*05d54b82SFabio Estevam #define MX6_IOM_DRAM_DQM0 0x020e02ec 15*05d54b82SFabio Estevam #define MX6_IOM_DRAM_DQM1 0x020e02f0 16*05d54b82SFabio Estevam #define MX6_IOM_DRAM_DQM2 0x020e02f4 17*05d54b82SFabio Estevam #define MX6_IOM_DRAM_DQM3 0x020e02f8 18*05d54b82SFabio Estevam 19*05d54b82SFabio Estevam #define MX6_IOM_DRAM_RAS 0x020e02fc 20*05d54b82SFabio Estevam #define MX6_IOM_DRAM_CAS 0x020e0300 21*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDODT0 0x020e0310 22*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDODT1 0x020e0314 23*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDBA2 0x020e0320 24*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDCKE0 0x020e0324 25*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDCKE1 0x020e0328 26*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDCLK_0 0x020e032c 27*05d54b82SFabio Estevam #define MX6_IOM_DRAM_RESET 0x020e0340 28*05d54b82SFabio Estevam 29*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDQS0 0x020e0330 30*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDQS1 0x020e0334 31*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDQS2 0x020e0338 32*05d54b82SFabio Estevam #define MX6_IOM_DRAM_SDQS3 0x020e033c 33*05d54b82SFabio Estevam 34*05d54b82SFabio Estevam #define MX6_IOM_GRP_ADDDS 0x020e05f4 35*05d54b82SFabio Estevam #define MX6_IOM_DDRMODE_CTL 0x020e05f8 36*05d54b82SFabio Estevam #define MX6_IOM_GRP_DDRPKE 0x020e05fc 37*05d54b82SFabio Estevam #define MX6_IOM_GRP_DDRMODE 0x020e0608 38*05d54b82SFabio Estevam #define MX6_IOM_GRP_B0DS 0x020e060c 39*05d54b82SFabio Estevam #define MX6_IOM_GRP_B1DS 0x020e0610 40*05d54b82SFabio Estevam #define MX6_IOM_GRP_CTLDS 0x020e0614 41*05d54b82SFabio Estevam #define MX6_IOM_GRP_DDR_TYPE 0x020e0618 42*05d54b82SFabio Estevam #define MX6_IOM_GRP_B2DS 0x020e061c 43*05d54b82SFabio Estevam #define MX6_IOM_GRP_B3DS 0x020e0620 44*05d54b82SFabio Estevam 45*05d54b82SFabio Estevam #endif /*__ASM_ARCH_MX6SX_DDR_H__ */ 46