1 /* 2 * Copyright (C) 2013 Boundary Devices Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __ASM_ARCH_MX6_DDR_H__ 7 #define __ASM_ARCH_MX6_DDR_H__ 8 9 #ifndef CONFIG_SPL_BUILD 10 #ifdef CONFIG_MX6Q 11 #include "mx6q-ddr.h" 12 #else 13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) 14 #include "mx6dl-ddr.h" 15 #else 16 #ifdef CONFIG_MX6SX 17 #include "mx6sx-ddr.h" 18 #else 19 #ifdef CONFIG_MX6UL 20 #include "mx6ul-ddr.h" 21 #else 22 #error "Please select cpu" 23 #endif /* CONFIG_MX6UL */ 24 #endif /* CONFIG_MX6SX */ 25 #endif /* CONFIG_MX6DL or CONFIG_MX6S */ 26 #endif /* CONFIG_MX6Q */ 27 #else 28 29 /* MMDC P0/P1 Registers */ 30 struct mmdc_p_regs { 31 u32 mdctl; 32 u32 mdpdc; 33 u32 mdotc; 34 u32 mdcfg0; 35 u32 mdcfg1; 36 u32 mdcfg2; 37 u32 mdmisc; 38 u32 mdscr; 39 u32 mdref; 40 u32 res1[2]; 41 u32 mdrwd; 42 u32 mdor; 43 u32 mdmrr; 44 u32 mdcfg3lp; 45 u32 mdmr4; 46 u32 mdasp; 47 u32 res2[239]; 48 u32 maarcr; 49 u32 mapsr; 50 u32 maexidr0; 51 u32 maexidr1; 52 u32 madpcr0; 53 u32 madpcr1; 54 u32 madpsr0; 55 u32 madpsr1; 56 u32 madpsr2; 57 u32 madpsr3; 58 u32 madpsr4; 59 u32 madpsr5; 60 u32 masbs0; 61 u32 masbs1; 62 u32 res3[2]; 63 u32 magenp; 64 u32 res4[239]; 65 u32 mpzqhwctrl; 66 u32 mpzqswctrl; 67 u32 mpwlgcr; 68 u32 mpwldectrl0; 69 u32 mpwldectrl1; 70 u32 mpwldlst; 71 u32 mpodtctrl; 72 u32 mprddqby0dl; 73 u32 mprddqby1dl; 74 u32 mprddqby2dl; 75 u32 mprddqby3dl; 76 u32 mpwrdqby0dl; 77 u32 mpwrdqby1dl; 78 u32 mpwrdqby2dl; 79 u32 mpwrdqby3dl; 80 u32 mpdgctrl0; 81 u32 mpdgctrl1; 82 u32 mpdgdlst0; 83 u32 mprddlctl; 84 u32 mprddlst; 85 u32 mpwrdlctl; 86 u32 mpwrdlst; 87 u32 mpsdctrl; 88 u32 mpzqlp2ctl; 89 u32 mprddlhwctl; 90 u32 mpwrdlhwctl; 91 u32 mprddlhwst0; 92 u32 mprddlhwst1; 93 u32 mpwrdlhwst0; 94 u32 mpwrdlhwst1; 95 u32 mpwlhwerr; 96 u32 mpdghwst0; 97 u32 mpdghwst1; 98 u32 mpdghwst2; 99 u32 mpdghwst3; 100 u32 mppdcmpr1; 101 u32 mppdcmpr2; 102 u32 mpswdar0; 103 u32 mpswdrdr0; 104 u32 mpswdrdr1; 105 u32 mpswdrdr2; 106 u32 mpswdrdr3; 107 u32 mpswdrdr4; 108 u32 mpswdrdr5; 109 u32 mpswdrdr6; 110 u32 mpswdrdr7; 111 u32 mpmur0; 112 u32 mpwrcadl; 113 u32 mpdccr; 114 }; 115 116 #define MX6UL_IOM_DDR_BASE 0x020e0200 117 struct mx6ul_iomux_ddr_regs { 118 u32 res1[17]; 119 u32 dram_dqm0; 120 u32 dram_dqm1; 121 u32 dram_ras; 122 u32 dram_cas; 123 u32 dram_cs0; 124 u32 dram_cs1; 125 u32 dram_sdwe_b; 126 u32 dram_odt0; 127 u32 dram_odt1; 128 u32 dram_sdba0; 129 u32 dram_sdba1; 130 u32 dram_sdba2; 131 u32 dram_sdcke0; 132 u32 dram_sdcke1; 133 u32 dram_sdclk_0; 134 u32 dram_sdqs0; 135 u32 dram_sdqs1; 136 u32 dram_reset; 137 }; 138 139 #define MX6UL_IOM_GRP_BASE 0x020e0400 140 struct mx6ul_iomux_grp_regs { 141 u32 res1[36]; 142 u32 grp_addds; 143 u32 grp_ddrmode_ctl; 144 u32 grp_b0ds; 145 u32 grp_ddrpk; 146 u32 grp_ctlds; 147 u32 grp_b1ds; 148 u32 grp_ddrhys; 149 u32 grp_ddrpke; 150 u32 grp_ddrmode; 151 u32 grp_ddr_type; 152 }; 153 154 #define MX6SX_IOM_DDR_BASE 0x020e0200 155 struct mx6sx_iomux_ddr_regs { 156 u32 res1[59]; 157 u32 dram_dqm0; 158 u32 dram_dqm1; 159 u32 dram_dqm2; 160 u32 dram_dqm3; 161 u32 dram_ras; 162 u32 dram_cas; 163 u32 res2[2]; 164 u32 dram_sdwe_b; 165 u32 dram_odt0; 166 u32 dram_odt1; 167 u32 dram_sdba0; 168 u32 dram_sdba1; 169 u32 dram_sdba2; 170 u32 dram_sdcke0; 171 u32 dram_sdcke1; 172 u32 dram_sdclk_0; 173 u32 dram_sdqs0; 174 u32 dram_sdqs1; 175 u32 dram_sdqs2; 176 u32 dram_sdqs3; 177 u32 dram_reset; 178 }; 179 180 #define MX6SX_IOM_GRP_BASE 0x020e0500 181 struct mx6sx_iomux_grp_regs { 182 u32 res1[61]; 183 u32 grp_addds; 184 u32 grp_ddrmode_ctl; 185 u32 grp_ddrpke; 186 u32 grp_ddrpk; 187 u32 grp_ddrhys; 188 u32 grp_ddrmode; 189 u32 grp_b0ds; 190 u32 grp_b1ds; 191 u32 grp_ctlds; 192 u32 grp_ddr_type; 193 u32 grp_b2ds; 194 u32 grp_b3ds; 195 }; 196 197 /* 198 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) 199 */ 200 #define MX6DQ_IOM_DDR_BASE 0x020e0500 201 struct mx6dq_iomux_ddr_regs { 202 u32 res1[3]; 203 u32 dram_sdqs5; 204 u32 dram_dqm5; 205 u32 dram_dqm4; 206 u32 dram_sdqs4; 207 u32 dram_sdqs3; 208 u32 dram_dqm3; 209 u32 dram_sdqs2; 210 u32 dram_dqm2; 211 u32 res2[16]; 212 u32 dram_cas; 213 u32 res3[2]; 214 u32 dram_ras; 215 u32 dram_reset; 216 u32 res4[2]; 217 u32 dram_sdclk_0; 218 u32 dram_sdba2; 219 u32 dram_sdcke0; 220 u32 dram_sdclk_1; 221 u32 dram_sdcke1; 222 u32 dram_sdodt0; 223 u32 dram_sdodt1; 224 u32 res5; 225 u32 dram_sdqs0; 226 u32 dram_dqm0; 227 u32 dram_sdqs1; 228 u32 dram_dqm1; 229 u32 dram_sdqs6; 230 u32 dram_dqm6; 231 u32 dram_sdqs7; 232 u32 dram_dqm7; 233 }; 234 235 #define MX6DQ_IOM_GRP_BASE 0x020e0700 236 struct mx6dq_iomux_grp_regs { 237 u32 res1[18]; 238 u32 grp_b7ds; 239 u32 grp_addds; 240 u32 grp_ddrmode_ctl; 241 u32 res2; 242 u32 grp_ddrpke; 243 u32 res3[6]; 244 u32 grp_ddrmode; 245 u32 res4[3]; 246 u32 grp_b0ds; 247 u32 grp_b1ds; 248 u32 grp_ctlds; 249 u32 res5; 250 u32 grp_b2ds; 251 u32 grp_ddr_type; 252 u32 grp_b3ds; 253 u32 grp_b4ds; 254 u32 grp_b5ds; 255 u32 grp_b6ds; 256 }; 257 258 #define MX6SDL_IOM_DDR_BASE 0x020e0400 259 struct mx6sdl_iomux_ddr_regs { 260 u32 res1[25]; 261 u32 dram_cas; 262 u32 res2[2]; 263 u32 dram_dqm0; 264 u32 dram_dqm1; 265 u32 dram_dqm2; 266 u32 dram_dqm3; 267 u32 dram_dqm4; 268 u32 dram_dqm5; 269 u32 dram_dqm6; 270 u32 dram_dqm7; 271 u32 dram_ras; 272 u32 dram_reset; 273 u32 res3[2]; 274 u32 dram_sdba2; 275 u32 dram_sdcke0; 276 u32 dram_sdcke1; 277 u32 dram_sdclk_0; 278 u32 dram_sdclk_1; 279 u32 dram_sdodt0; 280 u32 dram_sdodt1; 281 u32 dram_sdqs0; 282 u32 dram_sdqs1; 283 u32 dram_sdqs2; 284 u32 dram_sdqs3; 285 u32 dram_sdqs4; 286 u32 dram_sdqs5; 287 u32 dram_sdqs6; 288 u32 dram_sdqs7; 289 }; 290 291 #define MX6SDL_IOM_GRP_BASE 0x020e0700 292 struct mx6sdl_iomux_grp_regs { 293 u32 res1[18]; 294 u32 grp_b7ds; 295 u32 grp_addds; 296 u32 grp_ddrmode_ctl; 297 u32 grp_ddrpke; 298 u32 res2[2]; 299 u32 grp_ddrmode; 300 u32 grp_b0ds; 301 u32 res3; 302 u32 grp_ctlds; 303 u32 grp_b1ds; 304 u32 grp_ddr_type; 305 u32 grp_b2ds; 306 u32 grp_b3ds; 307 u32 grp_b4ds; 308 u32 grp_b5ds; 309 u32 res4; 310 u32 grp_b6ds; 311 }; 312 313 /* Device Information: Varies per DDR3 part number and speed grade */ 314 struct mx6_ddr3_cfg { 315 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ 316 u8 density; /* chip density (Gb) (1,2,4,8) */ 317 u8 width; /* bus width (bits) (4,8,16) */ 318 u8 banks; /* number of banks */ 319 u8 rowaddr; /* row address bits (11-16)*/ 320 u8 coladdr; /* col address bits (9-12) */ 321 u8 pagesz; /* page size (K) (1-2) */ 322 u16 trcd; /* tRCD=tRP=CL (ns*100) */ 323 u16 trcmin; /* tRC min (ns*100) */ 324 u16 trasmin; /* tRAS min (ns*100) */ 325 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ 326 }; 327 328 /* System Information: Varies per board design, layout, and term choices */ 329 struct mx6_ddr_sysinfo { 330 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ 331 u8 cs_density; /* density per chip select (Gb) */ 332 u8 ncs; /* number chip selects used (1|2) */ 333 char cs1_mirror;/* enable address mirror (0|1) */ 334 char bi_on; /* Bank interleaving enable */ 335 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ 336 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ 337 u8 ralat; /* Read Additional Latency (0-7) */ 338 u8 walat; /* Write Additional Latency (0-3) */ 339 u8 mif3_mode; /* Command prediction working mode */ 340 u8 rst_to_cke; /* Time from SDE enable to CKE rise */ 341 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ 342 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ 343 }; 344 345 /* 346 * Board specific calibration: 347 * This includes write leveling calibration values as well as DQS gating 348 * and read/write delays. These values are board/layout/device specific. 349 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 350 * (DOC-96412) to determine these values over a range of boards and 351 * temperatures. 352 */ 353 struct mx6_mmdc_calibration { 354 /* write leveling calibration */ 355 u32 p0_mpwldectrl0; 356 u32 p0_mpwldectrl1; 357 u32 p1_mpwldectrl0; 358 u32 p1_mpwldectrl1; 359 /* read DQS gating */ 360 u32 p0_mpdgctrl0; 361 u32 p0_mpdgctrl1; 362 u32 p1_mpdgctrl0; 363 u32 p1_mpdgctrl1; 364 /* read delay */ 365 u32 p0_mprddlctl; 366 u32 p1_mprddlctl; 367 /* write delay */ 368 u32 p0_mpwrdlctl; 369 u32 p1_mpwrdlctl; 370 }; 371 372 /* configure iomux (pinctl/padctl) */ 373 void mx6dq_dram_iocfg(unsigned width, 374 const struct mx6dq_iomux_ddr_regs *, 375 const struct mx6dq_iomux_grp_regs *); 376 void mx6sdl_dram_iocfg(unsigned width, 377 const struct mx6sdl_iomux_ddr_regs *, 378 const struct mx6sdl_iomux_grp_regs *); 379 void mx6sx_dram_iocfg(unsigned width, 380 const struct mx6sx_iomux_ddr_regs *, 381 const struct mx6sx_iomux_grp_regs *); 382 void mx6ul_dram_iocfg(unsigned width, 383 const struct mx6ul_iomux_ddr_regs *, 384 const struct mx6ul_iomux_grp_regs *); 385 386 /* configure mx6 mmdc registers */ 387 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, 388 const struct mx6_mmdc_calibration *, 389 const struct mx6_ddr3_cfg *); 390 391 #endif /* CONFIG_SPL_BUILD */ 392 393 #define MX6_MMDC_P0_MDCTL 0x021b0000 394 #define MX6_MMDC_P0_MDPDC 0x021b0004 395 #define MX6_MMDC_P0_MDOTC 0x021b0008 396 #define MX6_MMDC_P0_MDCFG0 0x021b000c 397 #define MX6_MMDC_P0_MDCFG1 0x021b0010 398 #define MX6_MMDC_P0_MDCFG2 0x021b0014 399 #define MX6_MMDC_P0_MDMISC 0x021b0018 400 #define MX6_MMDC_P0_MDSCR 0x021b001c 401 #define MX6_MMDC_P0_MDREF 0x021b0020 402 #define MX6_MMDC_P0_MDRWD 0x021b002c 403 #define MX6_MMDC_P0_MDOR 0x021b0030 404 #define MX6_MMDC_P0_MDASP 0x021b0040 405 #define MX6_MMDC_P0_MAPSR 0x021b0404 406 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 407 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c 408 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 409 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818 410 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c 411 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 412 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 413 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 414 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c 415 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 416 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 417 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 418 #define MX6_MMDC_P0_MPMUR0 0x021b08b8 419 420 #define MX6_MMDC_P1_MDCTL 0x021b4000 421 #define MX6_MMDC_P1_MDPDC 0x021b4004 422 #define MX6_MMDC_P1_MDOTC 0x021b4008 423 #define MX6_MMDC_P1_MDCFG0 0x021b400c 424 #define MX6_MMDC_P1_MDCFG1 0x021b4010 425 #define MX6_MMDC_P1_MDCFG2 0x021b4014 426 #define MX6_MMDC_P1_MDMISC 0x021b4018 427 #define MX6_MMDC_P1_MDSCR 0x021b401c 428 #define MX6_MMDC_P1_MDREF 0x021b4020 429 #define MX6_MMDC_P1_MDRWD 0x021b402c 430 #define MX6_MMDC_P1_MDOR 0x021b4030 431 #define MX6_MMDC_P1_MDASP 0x021b4040 432 #define MX6_MMDC_P1_MAPSR 0x021b4404 433 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 434 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c 435 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 436 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818 437 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c 438 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 439 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 440 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 441 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c 442 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 443 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 444 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 445 #define MX6_MMDC_P1_MPMUR0 0x021b48b8 446 447 #endif /*__ASM_ARCH_MX6_DDR_H__ */ 448