1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ 24 #define __ASM_ARCH_MX5_IMX_REGS_H__ 25 26 #if defined(CONFIG_MX51) 27 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 28 #define IPU_CTRL_BASE_ADDR 0x40000000 29 #define SPBA0_BASE_ADDR 0x70000000 30 #define AIPS1_BASE_ADDR 0x73F00000 31 #define AIPS2_BASE_ADDR 0x83F00000 32 #define CSD0_BASE_ADDR 0x90000000 33 #define CSD1_BASE_ADDR 0xA0000000 34 #define NFC_BASE_ADDR_AXI 0xCFFF0000 35 #define CS1_BASE_ADDR 0xB8000000 36 #elif defined(CONFIG_MX53) 37 #define IPU_CTRL_BASE_ADDR 0x18000000 38 #define SPBA0_BASE_ADDR 0x50000000 39 #define AIPS1_BASE_ADDR 0x53F00000 40 #define AIPS2_BASE_ADDR 0x63F00000 41 #define CSD0_BASE_ADDR 0x70000000 42 #define CSD1_BASE_ADDR 0xB0000000 43 #define NFC_BASE_ADDR_AXI 0xF7FF0000 44 #define IRAM_BASE_ADDR 0xF8000000 45 #define CS1_BASE_ADDR 0xF4000000 46 #else 47 #error "CPU_TYPE not defined" 48 #endif 49 50 #define IRAM_SIZE 0x00020000 /* 128 KB */ 51 52 /* 53 * SPBA global module enabled #0 54 */ 55 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 56 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 57 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) 58 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 59 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 60 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 61 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 62 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) 63 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) 64 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) 65 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) 66 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) 67 68 /* 69 * AIPS 1 70 */ 71 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 72 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 73 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 74 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 75 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 76 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 77 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 78 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 79 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 80 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 81 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 82 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 83 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 84 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 85 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 86 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) 87 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) 88 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) 89 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) 90 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) 91 92 #if defined(CONFIG_MX53) 93 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) 94 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) 95 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) 96 #endif 97 /* 98 * AIPS 2 99 */ 100 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 101 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 102 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) 103 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 104 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 105 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) 106 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) 107 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 108 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) 109 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 110 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 111 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) 112 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) 113 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) 114 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 115 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 116 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 117 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 118 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 119 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 120 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) 121 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) 122 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) 123 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) 124 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 125 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 126 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) 127 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) 128 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 129 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) 130 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) 131 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) 132 133 /* 134 * WEIM CSnGCR1 135 */ 136 #define CSEN 1 137 #define SWR (1 << 1) 138 #define SRD (1 << 2) 139 #define MUM (1 << 3) 140 #define WFL (1 << 4) 141 #define RFL (1 << 5) 142 #define CRE (1 << 6) 143 #define CREP (1 << 7) 144 #define BL(x) (((x) & 0x7) << 8) 145 #define WC (1 << 11) 146 #define BCD(x) (((x) & 0x3) << 12) 147 #define BCS(x) (((x) & 0x3) << 14) 148 #define DSZ(x) (((x) & 0x7) << 16) 149 #define SP (1 << 19) 150 #define CSREC(x) (((x) & 0x7) << 20) 151 #define AUS (1 << 23) 152 #define GBC(x) (((x) & 0x7) << 24) 153 #define WP (1 << 27) 154 #define PSZ(x) (((x) & 0x0f << 28) 155 156 /* 157 * WEIM CSnGCR2 158 */ 159 #define ADH(x) (((x) & 0x3)) 160 #define DAPS(x) (((x) & 0x0f << 4) 161 #define DAE (1 << 8) 162 #define DAP (1 << 9) 163 #define MUX16_BYP (1 << 12) 164 165 /* 166 * WEIM CSnRCR1 167 */ 168 #define RCSN(x) (((x) & 0x7)) 169 #define RCSA(x) (((x) & 0x7) << 4) 170 #define OEN(x) (((x) & 0x7) << 8) 171 #define OEA(x) (((x) & 0x7) << 12) 172 #define RADVN(x) (((x) & 0x7) << 16) 173 #define RAL (1 << 19) 174 #define RADVA(x) (((x) & 0x7) << 20) 175 #define RWSC(x) (((x) & 0x3f) << 24) 176 177 /* 178 * WEIM CSnRCR2 179 */ 180 #define RBEN(x) (((x) & 0x7)) 181 #define RBE (1 << 3) 182 #define RBEA(x) (((x) & 0x7) << 4) 183 #define RL(x) (((x) & 0x3) << 8) 184 #define PAT(x) (((x) & 0x7) << 12) 185 #define APR (1 << 15) 186 187 /* 188 * WEIM CSnWCR1 189 */ 190 #define WCSN(x) (((x) & 0x7)) 191 #define WCSA(x) (((x) & 0x7) << 3) 192 #define WEN(x) (((x) & 0x7) << 6) 193 #define WEA(x) (((x) & 0x7) << 9) 194 #define WBEN(x) (((x) & 0x7) << 12) 195 #define WBEA(x) (((x) & 0x7) << 15) 196 #define WADVN(x) (((x) & 0x7) << 18) 197 #define WADVA(x) (((x) & 0x7) << 21) 198 #define WWSC(x) (((x) & 0x3f) << 24) 199 #define WBED1 (1 << 30) 200 #define WAL (1 << 31) 201 202 /* 203 * WEIM CSnWCR2 204 */ 205 #define WBED 1 206 207 /* 208 * WEIM WCR 209 */ 210 #define BCM 1 211 #define GBCD(x) (((x) & 0x3) << 1) 212 #define INTEN (1 << 4) 213 #define INTPOL (1 << 5) 214 #define WDOG_EN (1 << 8) 215 #define WDOG_LIMIT(x) (((x) & 0x3) << 9) 216 217 /* 218 * Number of GPIO pins per port 219 */ 220 #define GPIO_NUM_PIN 32 221 222 #define IIM_SREV 0x24 223 #define ROM_SI_REV 0x48 224 225 #define NFC_BUF_SIZE 0x1000 226 227 /* M4IF */ 228 #define M4IF_FBPM0 0x40 229 #define M4IF_FIDBP 0x48 230 231 /* Assuming 24MHz input clock with doubler ON */ 232 /* MFI PDF */ 233 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) 234 #define DP_MFD_850 (48 - 1) 235 #define DP_MFN_850 41 236 237 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) 238 #define DP_MFD_800 (3 - 1) 239 #define DP_MFN_800 1 240 241 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) 242 #define DP_MFD_700 (24 - 1) 243 #define DP_MFN_700 7 244 245 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) 246 #define DP_MFD_665 (96 - 1) 247 #define DP_MFN_665 89 248 249 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) 250 #define DP_MFD_532 (24 - 1) 251 #define DP_MFN_532 13 252 253 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) 254 #define DP_MFD_400 (3 - 1) 255 #define DP_MFN_400 1 256 257 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) 258 #define DP_MFD_216 (4 - 1) 259 #define DP_MFN_216 3 260 261 #define CHIP_REV_1_0 0x10 262 #define CHIP_REV_1_1 0x11 263 #define CHIP_REV_2_0 0x20 264 #define CHIP_REV_2_5 0x25 265 #define CHIP_REV_3_0 0x30 266 267 #define BOARD_REV_1_0 0x0 268 #define BOARD_REV_2_0 0x1 269 270 #define IMX_IIM_BASE (IIM_BASE_ADDR) 271 272 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 273 #include <asm/types.h> 274 275 extern void imx_get_mac_from_fuse(unsigned char *mac); 276 277 #define __REG(x) (*((volatile u32 *)(x))) 278 #define __REG16(x) (*((volatile u16 *)(x))) 279 #define __REG8(x) (*((volatile u8 *)(x))) 280 281 struct clkctl { 282 u32 ccr; 283 u32 ccdr; 284 u32 csr; 285 u32 ccsr; 286 u32 cacrr; 287 u32 cbcdr; 288 u32 cbcmr; 289 u32 cscmr1; 290 u32 cscmr2; 291 u32 cscdr1; 292 u32 cs1cdr; 293 u32 cs2cdr; 294 u32 cdcdr; 295 u32 chsccdr; 296 u32 cscdr2; 297 u32 cscdr3; 298 u32 cscdr4; 299 u32 cwdr; 300 u32 cdhipr; 301 u32 cdcr; 302 u32 ctor; 303 u32 clpcr; 304 u32 cisr; 305 u32 cimr; 306 u32 ccosr; 307 u32 cgpr; 308 u32 ccgr0; 309 u32 ccgr1; 310 u32 ccgr2; 311 u32 ccgr3; 312 u32 ccgr4; 313 u32 ccgr5; 314 u32 ccgr6; 315 u32 cmeor; 316 }; 317 318 /* WEIM registers */ 319 struct weim { 320 u32 cs0gcr1; 321 u32 cs0gcr2; 322 u32 cs0rcr1; 323 u32 cs0rcr2; 324 u32 cs0wcr1; 325 u32 cs0wcr2; 326 u32 cs1gcr1; 327 u32 cs1gcr2; 328 u32 cs1rcr1; 329 u32 cs1rcr2; 330 u32 cs1wcr1; 331 u32 cs1wcr2; 332 u32 cs2gcr1; 333 u32 cs2gcr2; 334 u32 cs2rcr1; 335 u32 cs2rcr2; 336 u32 cs2wcr1; 337 u32 cs2wcr2; 338 u32 cs3gcr1; 339 u32 cs3gcr2; 340 u32 cs3rcr1; 341 u32 cs3rcr2; 342 u32 cs3wcr1; 343 u32 cs3wcr2; 344 u32 cs4gcr1; 345 u32 cs4gcr2; 346 u32 cs4rcr1; 347 u32 cs4rcr2; 348 u32 cs4wcr1; 349 u32 cs4wcr2; 350 u32 cs5gcr1; 351 u32 cs5gcr2; 352 u32 cs5rcr1; 353 u32 cs5rcr2; 354 u32 cs5wcr1; 355 u32 cs5wcr2; 356 u32 wcr; 357 u32 wiar; 358 u32 ear; 359 }; 360 361 #if defined(CONFIG_MX51) 362 struct iomuxc { 363 u32 gpr0; 364 u32 gpr1; 365 u32 omux0; 366 u32 omux1; 367 u32 omux2; 368 u32 omux3; 369 u32 omux4; 370 }; 371 #elif defined(CONFIG_MX53) 372 struct iomuxc { 373 u32 gpr0; 374 u32 gpr1; 375 u32 gpr2; 376 u32 omux0; 377 u32 omux1; 378 u32 omux2; 379 u32 omux3; 380 u32 omux4; 381 }; 382 #endif 383 384 /* GPIO Registers */ 385 struct gpio_regs { 386 u32 gpio_dr; 387 u32 gpio_dir; 388 u32 gpio_psr; 389 }; 390 391 /* System Reset Controller (SRC) */ 392 struct src { 393 u32 scr; 394 u32 sbmr; 395 u32 srsr; 396 u32 reserved1[2]; 397 u32 sisr; 398 u32 simr; 399 }; 400 401 /* CSPI registers */ 402 struct cspi_regs { 403 u32 rxdata; 404 u32 txdata; 405 u32 ctrl; 406 u32 cfg; 407 u32 intr; 408 u32 dma; 409 u32 stat; 410 u32 period; 411 }; 412 413 struct iim_regs { 414 u32 stat; 415 u32 statm; 416 u32 err; 417 u32 emask; 418 u32 fctl; 419 u32 ua; 420 u32 la; 421 u32 sdat; 422 u32 prev; 423 u32 srev; 424 u32 preg_p; 425 u32 scs0; 426 u32 scs1; 427 u32 scs2; 428 u32 scs3; 429 u32 res0[0x1f1]; 430 struct fuse_bank { 431 u32 fuse_regs[0x20]; 432 u32 fuse_rsvd[0xe0]; 433 } bank[4]; 434 }; 435 436 struct fuse_bank1_regs { 437 u32 fuse0_8[9]; 438 u32 mac_addr[6]; 439 u32 fuse15_31[0x11]; 440 }; 441 442 #endif /* __ASSEMBLER__*/ 443 444 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ 445