1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 24 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 25 26 #define MXC_CCM_BASE CCM_BASE_ADDR 27 28 /* DPLL register mapping structure */ 29 struct mxc_pll_reg { 30 u32 ctrl; 31 u32 config; 32 u32 op; 33 u32 mfd; 34 u32 mfn; 35 u32 mfn_minus; 36 u32 mfn_plus; 37 u32 hfs_op; 38 u32 hfs_mfd; 39 u32 hfs_mfn; 40 u32 mfn_togc; 41 u32 destat; 42 }; 43 44 /* Register maping of CCM*/ 45 struct mxc_ccm_reg { 46 u32 ccr; /* 0x0000 */ 47 u32 ccdr; 48 u32 csr; 49 u32 ccsr; 50 u32 cacrr; /* 0x0010*/ 51 u32 cbcdr; 52 u32 cbcmr; 53 u32 cscmr1; 54 u32 cscmr2; /* 0x0020 */ 55 u32 cscdr1; 56 u32 cs1cdr; 57 u32 cs2cdr; 58 u32 cdcdr; /* 0x0030 */ 59 u32 chscdr; 60 u32 cscdr2; 61 u32 cscdr3; 62 u32 cscdr4; /* 0x0040 */ 63 u32 cwdr; 64 u32 cdhipr; 65 u32 cdcr; 66 u32 ctor; /* 0x0050 */ 67 u32 clpcr; 68 u32 cisr; 69 u32 cimr; 70 u32 ccosr; /* 0x0060 */ 71 u32 cgpr; 72 u32 CCGR0; 73 u32 CCGR1; 74 u32 CCGR2; /* 0x0070 */ 75 u32 CCGR3; 76 u32 CCGR4; 77 u32 CCGR5; 78 u32 CCGR6; /* 0x0080 */ 79 #ifdef CONFIG_MX53 80 u32 CCGR7; /* 0x0084 */ 81 #endif 82 u32 cmeor; 83 }; 84 85 /* Define the bits in register CCSR */ 86 #if defined(CONFIG_MX51) 87 #define MXC_CCM_CCSR_LP_APM (0x1 << 9) 88 #elif defined(CONFIG_MX53) 89 #define MXC_CCM_CCSR_LP_APM (0x1 << 10) 90 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) 91 #endif 92 #define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 93 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) 94 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) 95 #define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) 96 #define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 97 #define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) 98 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) 99 #define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) 100 #define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 101 #define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) 102 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) 103 #define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) 104 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) 105 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) 106 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 107 108 /* Define the bits in register CACRR */ 109 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 110 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 111 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) 112 #define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) 113 114 /* Define the bits in register CBCDR */ 115 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) 116 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 117 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) 118 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) 119 #define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) 120 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) 121 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) 122 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 123 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) 124 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) 125 #define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) 126 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 127 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) 128 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) 129 #define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) 130 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 131 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) 132 #define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) 133 #define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) 134 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 135 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) 136 #define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) 137 #define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) 138 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 139 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 140 #define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) 141 #define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) 142 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 143 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 144 #define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) 145 #define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) 146 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 147 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) 148 #define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) 149 #define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) 150 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 151 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) 152 #define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) 153 #define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) 154 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 155 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 156 #define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) 157 #define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) 158 159 /* Define the bits in register CSCMR1 */ 160 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 161 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) 162 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) 163 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) 164 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 165 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) 166 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) 167 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) 168 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) 169 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 170 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) 171 #define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) 172 #define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) 173 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 174 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) 175 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) 176 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) 177 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 178 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 179 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) 180 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) 181 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 182 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 183 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 184 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 185 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) 186 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) 187 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 188 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 189 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) 190 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 191 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 192 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 193 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) 194 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 195 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) 196 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) 197 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 198 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) 199 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) 200 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 201 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) 202 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) 203 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 204 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) 205 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) 206 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 207 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 208 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) 209 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) 210 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) 211 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) 212 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 213 214 /* Define the bits in register CSCDR2 */ 215 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 216 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) 217 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) 218 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) 219 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 220 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) 221 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) 222 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) 223 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 224 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) 225 #define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) 226 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 227 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 228 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) 229 #define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) 230 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) 231 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 232 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) 233 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) 234 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) 235 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 236 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F 237 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) 238 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) 239 240 /* Define the bits in register CBCMR */ 241 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 242 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 243 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) 244 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 245 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 246 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) 247 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) 248 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 249 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 250 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) 251 #define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) 252 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) 253 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 254 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) 255 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) 256 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 257 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 258 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) 259 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) 260 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) 261 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 262 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) 263 #define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) 264 #define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 265 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) 266 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) 267 268 /* Define the bits in register CSCDR1 */ 269 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 270 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 271 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) 272 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) 273 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 274 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 275 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) 276 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) 277 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 278 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 279 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) 280 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 281 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 282 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) 283 #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) 284 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) 285 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 286 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) 287 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) 288 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) 289 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 290 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 291 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) 292 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) 293 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 294 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 295 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) 296 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) 297 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 298 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) 299 #define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) 300 #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) 301 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 302 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 303 #define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) 304 #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) 305 306 /* Define the bits in register CCDR */ 307 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) 308 309 /* Define the bits in register CCGRx */ 310 #define MXC_CCM_CCGR_CG_MASK 0x3 311 #define MXC_CCM_CCGR_CG_OFF 0x0 312 #define MXC_CCM_CCGR_CG_RUN_ON 0x1 313 #define MXC_CCM_CCGR_CG_ON 0x3 314 315 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 316 #define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) 317 #define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 318 #define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) 319 #define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 320 #define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) 321 #define MXC_CCM_CCGR0_TZIC_OFFSET 6 322 #define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) 323 #define MXC_CCM_CCGR0_DAP_OFFSET 8 324 #define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) 325 #define MXC_CCM_CCGR0_TPIU_OFFSET 10 326 #define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) 327 #define MXC_CCM_CCGR0_CTI2_OFFSET 12 328 #define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) 329 #define MXC_CCM_CCGR0_CTI3_OFFSET 14 330 #define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) 331 #define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 332 #define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) 333 #define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 334 #define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) 335 #define MXC_CCM_CCGR0_ROMCP_OFFSET 20 336 #define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) 337 #define MXC_CCM_CCGR0_ROM_OFFSET 22 338 #define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) 339 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 340 #define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) 341 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 342 #define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) 343 #define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 344 #define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) 345 #define MXC_CCM_CCGR0_IIM_OFFSET 30 346 #define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) 347 348 #define MXC_CCM_CCGR1_TMAX1_OFFSET 0 349 #define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) 350 #define MXC_CCM_CCGR1_TMAX2_OFFSET 2 351 #define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) 352 #define MXC_CCM_CCGR1_TMAX3_OFFSET 4 353 #define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) 354 #define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 355 #define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) 356 #define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 357 #define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) 358 #define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 359 #define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) 360 #define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 361 #define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) 362 #define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 363 #define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) 364 #define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 365 #define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) 366 #define MXC_CCM_CCGR1_I2C1_OFFSET 18 367 #define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) 368 #define MXC_CCM_CCGR1_I2C2_OFFSET 20 369 #define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) 370 #if defined(CONFIG_MX51) 371 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 372 #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) 373 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 374 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) 375 #elif defined(CONFIG_MX53) 376 #define MXC_CCM_CCGR1_I2C3_OFFSET 22 377 #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) 378 #endif 379 #define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 380 #define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) 381 #define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 382 #define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) 383 #define MXC_CCM_CCGR1_SCC_OFFSET 30 384 #define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) 385 386 #if defined(CONFIG_MX51) 387 #define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 388 #define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) 389 #endif 390 #define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 391 #define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) 392 #define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 393 #define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) 394 #define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 395 #define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) 396 #define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 397 #define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) 398 #define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 399 #define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) 400 #define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 401 #define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) 402 #define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 403 #define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) 404 #define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 405 #define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) 406 #define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 407 #define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) 408 #define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 409 #define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) 410 #define MXC_CCM_CCGR2_OWIRE_OFFSET 22 411 #define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) 412 #define MXC_CCM_CCGR2_FEC_OFFSET 24 413 #define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) 414 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 415 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) 416 #define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 417 #define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) 418 #define MXC_CCM_CCGR2_TVE_OFFSET 30 419 #define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) 420 421 #define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 422 #define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) 423 #define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 424 #define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) 425 #define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 426 #define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) 427 #define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 428 #define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) 429 #define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 430 #define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) 431 #define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 432 #define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) 433 #define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 434 #define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) 435 #define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 436 #define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) 437 #define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 438 #define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) 439 #define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 440 #define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) 441 #define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 442 #define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) 443 #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 444 #define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) 445 #define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 446 #define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) 447 #define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 448 #define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) 449 #define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 450 #define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) 451 #define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 452 #define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) 453 454 #define MXC_CCM_CCGR4_PATA_OFFSET 0 455 #define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) 456 #if defined(CONFIG_MX51) 457 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 458 #define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) 459 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 460 #define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) 461 #elif defined(CONFIG_MX53) 462 #define MXC_CCM_CCGR4_SATA_OFFSET 2 463 #define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) 464 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 465 #define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) 466 #define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 467 #define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) 468 #define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 469 #define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) 470 #define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 471 #define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) 472 #endif 473 #define MXC_CCM_CCGR4_SAHARA_OFFSET 14 474 #define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) 475 #define MXC_CCM_CCGR4_RTIC_OFFSET 16 476 #define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) 477 #define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 478 #define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) 479 #define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 480 #define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) 481 #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 482 #define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) 483 #define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 484 #define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) 485 #define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 486 #define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) 487 #define MXC_CCM_CCGR4_SRTC_OFFSET 28 488 #define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) 489 #define MXC_CCM_CCGR4_SDMA_OFFSET 30 490 #define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) 491 492 #define MXC_CCM_CCGR5_SPBA_OFFSET 0 493 #define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) 494 #define MXC_CCM_CCGR5_GPU_OFFSET 2 495 #define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) 496 #define MXC_CCM_CCGR5_GARB_OFFSET 4 497 #define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) 498 #define MXC_CCM_CCGR5_VPU_OFFSET 6 499 #define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) 500 #define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 501 #define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) 502 #define MXC_CCM_CCGR5_IPU_OFFSET 10 503 #define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) 504 #if defined(CONFIG_MX51) 505 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 506 #define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) 507 #elif defined(CONFIG_MX53) 508 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 509 #define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) 510 #endif 511 #define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 512 #define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) 513 #define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 514 #define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) 515 #define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 516 #define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) 517 #define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 518 #define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) 519 #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 520 #define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) 521 #define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 522 #define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) 523 #define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 524 #define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) 525 #if defined(CONFIG_MX51) 526 #define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 527 #define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) 528 #endif 529 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 530 #define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) 531 532 #if defined(CONFIG_MX53) 533 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 534 #define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) 535 #define MXC_CCM_CCGR6_OCRAM_OFFSET 2 536 #define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) 537 #endif 538 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 539 #define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) 540 #if defined(CONFIG_MX51) 541 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 542 #define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) 543 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 544 #define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) 545 #elif defined(CONFIG_MX53) 546 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 547 #define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) 548 #endif 549 #define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 550 #define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) 551 #define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 552 #define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) 553 #define MXC_CCM_CCGR6_GPU2D_OFFSET 14 554 #define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) 555 #if defined(CONFIG_MX53) 556 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 557 #define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) 558 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 559 #define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) 560 #define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 561 #define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) 562 #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 563 #define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) 564 #define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 565 #define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) 566 #define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 567 #define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) 568 #define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 569 #define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) 570 #define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 571 #define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) 572 573 #define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 574 #define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) 575 #define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 576 #define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) 577 #define MXC_CCM_CCGR7_MLB_OFFSET 4 578 #define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) 579 #define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 580 #define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) 581 #define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 582 #define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) 583 #define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 584 #define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) 585 #define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 586 #define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) 587 #define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 588 #define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) 589 #endif 590 591 /* Define the bits in register CLPCR */ 592 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) 593 594 #define MXC_DPLLC_CTL_HFSM (1 << 7) 595 #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) 596 597 #define MXC_DPLLC_OP_PDF_MASK 0xf 598 #define MXC_DPLLC_OP_MFI_OFFSET 4 599 #define MXC_DPLLC_OP_MFI_MASK (0xf << 4) 600 #define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) 601 #define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) 602 603 #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff 604 605 #define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff 606 607 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ 608