1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 24 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 25 26 #define MXC_CCM_BASE CCM_BASE_ADDR 27 28 /* DPLL register mapping structure */ 29 struct mxc_pll_reg { 30 u32 ctrl; 31 u32 config; 32 u32 op; 33 u32 mfd; 34 u32 mfn; 35 u32 mfn_minus; 36 u32 mfn_plus; 37 u32 hfs_op; 38 u32 hfs_mfd; 39 u32 hfs_mfn; 40 u32 mfn_togc; 41 u32 destat; 42 }; 43 44 /* Register maping of CCM*/ 45 struct mxc_ccm_reg { 46 u32 ccr; /* 0x0000 */ 47 u32 ccdr; 48 u32 csr; 49 u32 ccsr; 50 u32 cacrr; /* 0x0010*/ 51 u32 cbcdr; 52 u32 cbcmr; 53 u32 cscmr1; 54 u32 cscmr2; /* 0x0020 */ 55 u32 cscdr1; 56 u32 cs1cdr; 57 u32 cs2cdr; 58 u32 cdcdr; /* 0x0030 */ 59 u32 chscdr; 60 u32 cscdr2; 61 u32 cscdr3; 62 u32 cscdr4; /* 0x0040 */ 63 u32 cwdr; 64 u32 cdhipr; 65 u32 cdcr; 66 u32 ctor; /* 0x0050 */ 67 u32 clpcr; 68 u32 cisr; 69 u32 cimr; 70 u32 ccosr; /* 0x0060 */ 71 u32 cgpr; 72 u32 CCGR0; 73 u32 CCGR1; 74 u32 CCGR2; /* 0x0070 */ 75 u32 CCGR3; 76 u32 CCGR4; 77 u32 CCGR5; 78 u32 CCGR6; /* 0x0080 */ 79 #ifdef CONFIG_MX53 80 u32 CCGR7; /* 0x0084 */ 81 #endif 82 u32 cmeor; 83 }; 84 85 /* Define the bits in register CACRR */ 86 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 87 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 88 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) 89 #define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) 90 91 /* Define the bits in register CBCDR */ 92 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) 93 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 94 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) 95 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) 96 #define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) 97 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) 98 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) 99 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 100 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) 101 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) 102 #define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) 103 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 104 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) 105 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) 106 #define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) 107 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 108 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) 109 #define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) 110 #define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) 111 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 112 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) 113 #define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) 114 #define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) 115 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 116 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 117 #define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) 118 #define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) 119 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 120 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 121 #define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) 122 #define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) 123 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 124 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) 125 #define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) 126 #define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) 127 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 128 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) 129 #define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) 130 #define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) 131 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 132 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 133 #define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) 134 #define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) 135 136 /* Define the bits in register CSCMR1 */ 137 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 138 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) 139 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) 140 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) 141 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 142 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) 143 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) 144 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) 145 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) 146 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 147 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) 148 #define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) 149 #define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) 150 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 151 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) 152 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) 153 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) 154 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 155 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 156 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) 157 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) 158 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 159 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 160 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 161 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 162 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) 163 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) 164 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 165 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 166 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) 167 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 168 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 169 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 170 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) 171 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 172 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) 173 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) 174 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 175 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) 176 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) 177 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 178 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) 179 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) 180 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 181 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) 182 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) 183 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 184 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 185 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) 186 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) 187 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) 188 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) 189 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 190 191 /* Define the bits in register CSCDR2 */ 192 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 193 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) 194 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) 195 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) 196 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 197 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) 198 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) 199 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) 200 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 201 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) 202 #define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) 203 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 204 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 205 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) 206 #define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) 207 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) 208 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 209 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) 210 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) 211 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) 212 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 213 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F 214 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) 215 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) 216 217 /* Define the bits in register CBCMR */ 218 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 219 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 220 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) 221 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 222 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 223 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) 224 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) 225 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 226 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 227 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) 228 #define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) 229 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) 230 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 231 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) 232 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) 233 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 234 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 235 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) 236 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) 237 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) 238 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 239 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) 240 #define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) 241 #define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 242 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) 243 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) 244 245 /* Define the bits in register CSCDR1 */ 246 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 247 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 248 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) 249 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) 250 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 251 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 252 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) 253 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) 254 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 255 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 256 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) 257 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 258 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 259 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) 260 #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) 261 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) 262 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 263 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) 264 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) 265 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) 266 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 267 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 268 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) 269 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) 270 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 271 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 272 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) 273 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) 274 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 275 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) 276 #define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) 277 #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) 278 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 279 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 280 #define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) 281 #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) 282 283 /* Define the bits in register CCDR */ 284 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) 285 286 /* Define the bits in register CCGRx */ 287 #define MXC_CCM_CCGR_CG_MASK 0x3 288 #define MXC_CCM_CCGR_CG_OFF 0x0 289 #define MXC_CCM_CCGR_CG_RUN_ON 0x1 290 #define MXC_CCM_CCGR_CG_ON 0x3 291 292 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 293 #define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) 294 #define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 295 #define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) 296 #define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 297 #define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) 298 #define MXC_CCM_CCGR0_TZIC_OFFSET 6 299 #define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) 300 #define MXC_CCM_CCGR0_DAP_OFFSET 8 301 #define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) 302 #define MXC_CCM_CCGR0_TPIU_OFFSET 10 303 #define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) 304 #define MXC_CCM_CCGR0_CTI2_OFFSET 12 305 #define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) 306 #define MXC_CCM_CCGR0_CTI3_OFFSET 14 307 #define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) 308 #define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 309 #define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) 310 #define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 311 #define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) 312 #define MXC_CCM_CCGR0_ROMCP_OFFSET 20 313 #define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) 314 #define MXC_CCM_CCGR0_ROM_OFFSET 22 315 #define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) 316 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 317 #define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) 318 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 319 #define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) 320 #define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 321 #define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) 322 #define MXC_CCM_CCGR0_IIM_OFFSET 30 323 #define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) 324 325 #define MXC_CCM_CCGR1_TMAX1_OFFSET 0 326 #define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) 327 #define MXC_CCM_CCGR1_TMAX2_OFFSET 2 328 #define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) 329 #define MXC_CCM_CCGR1_TMAX3_OFFSET 4 330 #define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) 331 #define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 332 #define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) 333 #define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 334 #define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) 335 #define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 336 #define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) 337 #define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 338 #define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) 339 #define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 340 #define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) 341 #define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 342 #define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) 343 #define MXC_CCM_CCGR1_I2C1_OFFSET 18 344 #define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) 345 #define MXC_CCM_CCGR1_I2C2_OFFSET 20 346 #define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) 347 #if defined(CONFIG_MX51) 348 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 349 #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) 350 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 351 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) 352 #elif defined(CONFIG_MX53) 353 #define MXC_CCM_CCGR1_I2C3_OFFSET 22 354 #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) 355 #endif 356 #define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 357 #define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) 358 #define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 359 #define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) 360 #define MXC_CCM_CCGR1_SCC_OFFSET 30 361 #define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) 362 363 #if defined(CONFIG_MX51) 364 #define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 365 #define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) 366 #endif 367 #define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 368 #define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) 369 #define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 370 #define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) 371 #define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 372 #define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) 373 #define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 374 #define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) 375 #define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 376 #define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) 377 #define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 378 #define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) 379 #define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 380 #define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) 381 #define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 382 #define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) 383 #define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 384 #define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) 385 #define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 386 #define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) 387 #define MXC_CCM_CCGR2_OWIRE_OFFSET 22 388 #define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) 389 #define MXC_CCM_CCGR2_FEC_OFFSET 24 390 #define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) 391 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 392 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) 393 #define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 394 #define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) 395 #define MXC_CCM_CCGR2_TVE_OFFSET 30 396 #define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) 397 398 #define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 399 #define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) 400 #define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 401 #define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) 402 #define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 403 #define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) 404 #define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 405 #define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) 406 #define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 407 #define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) 408 #define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 409 #define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) 410 #define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 411 #define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) 412 #define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 413 #define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) 414 #define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 415 #define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) 416 #define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 417 #define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) 418 #define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 419 #define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) 420 #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 421 #define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) 422 #define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 423 #define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) 424 #define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 425 #define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) 426 #define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 427 #define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) 428 #define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 429 #define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) 430 431 #define MXC_CCM_CCGR4_PATA_OFFSET 0 432 #define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) 433 #if defined(CONFIG_MX51) 434 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 435 #define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) 436 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 437 #define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) 438 #elif defined(CONFIG_MX53) 439 #define MXC_CCM_CCGR4_SATA_OFFSET 2 440 #define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) 441 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 442 #define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) 443 #define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 444 #define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) 445 #define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 446 #define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) 447 #define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 448 #define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) 449 #endif 450 #define MXC_CCM_CCGR4_SAHARA_OFFSET 14 451 #define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) 452 #define MXC_CCM_CCGR4_RTIC_OFFSET 16 453 #define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) 454 #define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 455 #define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) 456 #define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 457 #define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) 458 #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 459 #define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) 460 #define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 461 #define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) 462 #define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 463 #define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) 464 #define MXC_CCM_CCGR4_SRTC_OFFSET 28 465 #define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) 466 #define MXC_CCM_CCGR4_SDMA_OFFSET 30 467 #define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) 468 469 #define MXC_CCM_CCGR5_SPBA_OFFSET 0 470 #define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) 471 #define MXC_CCM_CCGR5_GPU_OFFSET 2 472 #define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) 473 #define MXC_CCM_CCGR5_GARB_OFFSET 4 474 #define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) 475 #define MXC_CCM_CCGR5_VPU_OFFSET 6 476 #define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) 477 #define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 478 #define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) 479 #define MXC_CCM_CCGR5_IPU_OFFSET 10 480 #define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) 481 #if defined(CONFIG_MX51) 482 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 483 #define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) 484 #elif defined(CONFIG_MX53) 485 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 486 #define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) 487 #endif 488 #define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 489 #define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) 490 #define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 491 #define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) 492 #define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 493 #define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) 494 #define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 495 #define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) 496 #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 497 #define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) 498 #define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 499 #define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) 500 #define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 501 #define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) 502 #if defined(CONFIG_MX51) 503 #define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 504 #define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) 505 #endif 506 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 507 #define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) 508 509 #if defined(CONFIG_MX53) 510 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 511 #define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) 512 #define MXC_CCM_CCGR6_OCRAM_OFFSET 2 513 #define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) 514 #endif 515 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 516 #define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) 517 #if defined(CONFIG_MX51) 518 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 519 #define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) 520 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 521 #define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) 522 #elif defined(CONFIG_MX53) 523 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 524 #define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) 525 #endif 526 #define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 527 #define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) 528 #define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 529 #define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) 530 #define MXC_CCM_CCGR6_GPU2D_OFFSET 14 531 #define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) 532 #if defined(CONFIG_MX53) 533 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 534 #define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) 535 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 536 #define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) 537 #define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 538 #define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) 539 #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 540 #define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) 541 #define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 542 #define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) 543 #define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 544 #define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) 545 #define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 546 #define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) 547 #define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 548 #define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) 549 550 #define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 551 #define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) 552 #define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 553 #define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) 554 #define MXC_CCM_CCGR7_MLB_OFFSET 4 555 #define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) 556 #define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 557 #define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) 558 #define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 559 #define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) 560 #define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 561 #define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) 562 #define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 563 #define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) 564 #define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 565 #define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) 566 #endif 567 568 /* Define the bits in register CLPCR */ 569 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) 570 571 #define MXC_DPLLC_CTL_HFSM (1 << 7) 572 #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) 573 574 #define MXC_DPLLC_OP_PDF_MASK 0xf 575 #define MXC_DPLLC_OP_MFI_OFFSET 4 576 #define MXC_DPLLC_OP_MFI_MASK (0xf << 4) 577 #define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) 578 #define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) 579 580 #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff 581 582 #define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff 583 584 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ 585