1*03c22449SZhuoyu Zhang /* 2*03c22449SZhuoyu Zhang * Copyright 2015 Freescale Semiconductor, Inc. 3*03c22449SZhuoyu Zhang * 4*03c22449SZhuoyu Zhang * SPDX-License-Identifier: GPL-2.0+ 5*03c22449SZhuoyu Zhang */ 6*03c22449SZhuoyu Zhang 7*03c22449SZhuoyu Zhang #ifndef __FSL_LS102XA_DEVDIS_H_ 8*03c22449SZhuoyu Zhang #define __FSL_LS102XA_DEVDIS_H_ 9*03c22449SZhuoyu Zhang 10*03c22449SZhuoyu Zhang #include <fsl_devdis.h> 11*03c22449SZhuoyu Zhang 12*03c22449SZhuoyu Zhang const struct devdis_table devdis_tbl[] = { 13*03c22449SZhuoyu Zhang { "pbl", 0x0, 0x80000000 }, /* PBL */ 14*03c22449SZhuoyu Zhang { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ 15*03c22449SZhuoyu Zhang { "qdma", 0x0, 0x800000 }, /* qDMA */ 16*03c22449SZhuoyu Zhang { "edma", 0x0, 0x400000 }, /* eDMA */ 17*03c22449SZhuoyu Zhang { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ 18*03c22449SZhuoyu Zhang { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ 19*03c22449SZhuoyu Zhang { "sata", 0x0, 0x8000 }, /* SATA */ 20*03c22449SZhuoyu Zhang { "sec", 0x0, 0x200 }, /* SEC */ 21*03c22449SZhuoyu Zhang { "dcu", 0x0, 0x2 }, /* Display controller Unit */ 22*03c22449SZhuoyu Zhang { "qe", 0x0, 0x1 }, /* QUICC Engine */ 23*03c22449SZhuoyu Zhang { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ 24*03c22449SZhuoyu Zhang { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ 25*03c22449SZhuoyu Zhang { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ 26*03c22449SZhuoyu Zhang { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ 27*03c22449SZhuoyu Zhang { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ 28*03c22449SZhuoyu Zhang { "duart1", 0x3, 0x20000000 }, /* DUART1 */ 29*03c22449SZhuoyu Zhang { "duart2", 0x3, 0x10000000 }, /* DUART2 */ 30*03c22449SZhuoyu Zhang { "qspi", 0x3, 0x8000000 }, /* QSPI */ 31*03c22449SZhuoyu Zhang { "ddr", 0x4, 0x80000000 }, /* DDR */ 32*03c22449SZhuoyu Zhang { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ 33*03c22449SZhuoyu Zhang { "ifc", 0x4, 0x800000 }, /* IFC */ 34*03c22449SZhuoyu Zhang { "gpio", 0x4, 0x400000 }, /* GPIO */ 35*03c22449SZhuoyu Zhang { "dbg", 0x4, 0x200000 }, /* DBG */ 36*03c22449SZhuoyu Zhang { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ 37*03c22449SZhuoyu Zhang { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ 38*03c22449SZhuoyu Zhang { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ 39*03c22449SZhuoyu Zhang { "secmon", 0x4, 0x4000 }, /* Security Monitor */ 40*03c22449SZhuoyu Zhang { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ 41*03c22449SZhuoyu Zhang { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ 42*03c22449SZhuoyu Zhang { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ 43*03c22449SZhuoyu Zhang { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ 44*03c22449SZhuoyu Zhang { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ 45*03c22449SZhuoyu Zhang { "asrc", 0x4, 0x20 }, /* ASRC */ 46*03c22449SZhuoyu Zhang { "spdif", 0x4, 0x10 }, /* SPDIF */ 47*03c22449SZhuoyu Zhang { "i2c1", 0x4, 0x4 }, /* I2C1 */ 48*03c22449SZhuoyu Zhang { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ 49*03c22449SZhuoyu Zhang { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ 50*03c22449SZhuoyu Zhang }; 51*03c22449SZhuoyu Zhang 52*03c22449SZhuoyu Zhang #endif 53