1*52f69f81SVladimir Zapolskiy /* 2*52f69f81SVladimir Zapolskiy * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*52f69f81SVladimir Zapolskiy * 4*52f69f81SVladimir Zapolskiy * This program is free software; you can redistribute it and/or 5*52f69f81SVladimir Zapolskiy * modify it under the terms of the GNU General Public License 6*52f69f81SVladimir Zapolskiy * as published by the Free Software Foundation; either version 2 7*52f69f81SVladimir Zapolskiy * of the License, or (at your option) any later version. 8*52f69f81SVladimir Zapolskiy * 9*52f69f81SVladimir Zapolskiy * This program is distributed in the hope that it will be useful, 10*52f69f81SVladimir Zapolskiy * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*52f69f81SVladimir Zapolskiy * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*52f69f81SVladimir Zapolskiy * GNU General Public License for more details. 13*52f69f81SVladimir Zapolskiy * 14*52f69f81SVladimir Zapolskiy * You should have received a copy of the GNU General Public License 15*52f69f81SVladimir Zapolskiy * along with this program; if not, write to the Free Software 16*52f69f81SVladimir Zapolskiy * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17*52f69f81SVladimir Zapolskiy * MA 02110-1301, USA. 18*52f69f81SVladimir Zapolskiy */ 19*52f69f81SVladimir Zapolskiy 20*52f69f81SVladimir Zapolskiy #ifndef _LPC32XX_TIMER_H 21*52f69f81SVladimir Zapolskiy #define _LPC32XX_TIMER_H 22*52f69f81SVladimir Zapolskiy 23*52f69f81SVladimir Zapolskiy #include <asm/types.h> 24*52f69f81SVladimir Zapolskiy 25*52f69f81SVladimir Zapolskiy /* Timer/Counter Registers */ 26*52f69f81SVladimir Zapolskiy struct timer_regs { 27*52f69f81SVladimir Zapolskiy u32 ir; /* Interrupt Register */ 28*52f69f81SVladimir Zapolskiy u32 tcr; /* Timer Control Register */ 29*52f69f81SVladimir Zapolskiy u32 tc; /* Timer Counter */ 30*52f69f81SVladimir Zapolskiy u32 pr; /* Prescale Register */ 31*52f69f81SVladimir Zapolskiy u32 pc; /* Prescale Counter */ 32*52f69f81SVladimir Zapolskiy u32 mcr; /* Match Control Register */ 33*52f69f81SVladimir Zapolskiy u32 mr[4]; /* Match Registers */ 34*52f69f81SVladimir Zapolskiy u32 ccr; /* Capture Control Register */ 35*52f69f81SVladimir Zapolskiy u32 cr[4]; /* Capture Registers */ 36*52f69f81SVladimir Zapolskiy u32 emr; /* External Match Register */ 37*52f69f81SVladimir Zapolskiy u32 reserved[12]; 38*52f69f81SVladimir Zapolskiy u32 ctcr; /* Count Control Register */ 39*52f69f81SVladimir Zapolskiy }; 40*52f69f81SVladimir Zapolskiy 41*52f69f81SVladimir Zapolskiy /* Timer/Counter Interrupt Register bits */ 42*52f69f81SVladimir Zapolskiy #define TIMER_IR_CR(n) (1 << ((n) + 4)) 43*52f69f81SVladimir Zapolskiy #define TIMER_IR_MR(n) (1 << (n)) 44*52f69f81SVladimir Zapolskiy 45*52f69f81SVladimir Zapolskiy /* Timer/Counter Timer Control Register bits */ 46*52f69f81SVladimir Zapolskiy #define TIMER_TCR_COUNTER_RESET (1 << 1) 47*52f69f81SVladimir Zapolskiy #define TIMER_TCR_COUNTER_ENABLE (1 << 0) 48*52f69f81SVladimir Zapolskiy #define TIMER_TCR_COUNTER_DISABLE (0 << 0) 49*52f69f81SVladimir Zapolskiy 50*52f69f81SVladimir Zapolskiy /* Timer/Counter Match Control Register bits */ 51*52f69f81SVladimir Zapolskiy #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) 52*52f69f81SVladimir Zapolskiy #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) 53*52f69f81SVladimir Zapolskiy #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) 54*52f69f81SVladimir Zapolskiy 55*52f69f81SVladimir Zapolskiy /* Timer/Counter Capture Control Register bits */ 56*52f69f81SVladimir Zapolskiy #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) 57*52f69f81SVladimir Zapolskiy #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) 58*52f69f81SVladimir Zapolskiy #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) 59*52f69f81SVladimir Zapolskiy 60*52f69f81SVladimir Zapolskiy /* Timer/Counter External Match Register bits */ 61*52f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) 62*52f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) 63*52f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) 64*52f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) 65*52f69f81SVladimir Zapolskiy #define TIMER_EMR_EM(n) (1 << (n)) 66*52f69f81SVladimir Zapolskiy 67*52f69f81SVladimir Zapolskiy /* Timer/Counter Count Control Register bits */ 68*52f69f81SVladimir Zapolskiy #define TIMER_CTCR_INPUT(n) ((n) << 2) 69*52f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) 70*52f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) 71*52f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) 72*52f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_TIMER (0x0 << 0) 73*52f69f81SVladimir Zapolskiy 74*52f69f81SVladimir Zapolskiy #endif /* _LPC32XX_TIMER_H */ 75