1412ae53aSAlbert ARIBAUD \(3ADEV\) /* 2412ae53aSAlbert ARIBAUD \(3ADEV\) * LPC32xx MUX interface 3412ae53aSAlbert ARIBAUD \(3ADEV\) * 4412ae53aSAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2015 DENX Software Engineering GmbH 5412ae53aSAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6412ae53aSAlbert ARIBAUD \(3ADEV\) * 7412ae53aSAlbert ARIBAUD \(3ADEV\) * SPDX-License-Identifier: GPL-2.0+ 8412ae53aSAlbert ARIBAUD \(3ADEV\) */ 9412ae53aSAlbert ARIBAUD \(3ADEV\) 10412ae53aSAlbert ARIBAUD \(3ADEV\) /** 11412ae53aSAlbert ARIBAUD \(3ADEV\) * MUX register map for LPC32xx 12412ae53aSAlbert ARIBAUD \(3ADEV\) */ 13412ae53aSAlbert ARIBAUD \(3ADEV\) 14412ae53aSAlbert ARIBAUD \(3ADEV\) struct mux_regs { 15*d75b532aSSylvain Lemieux u32 reserved1[10]; 16*d75b532aSSylvain Lemieux u32 p2_mux_set; 17*d75b532aSSylvain Lemieux u32 p2_mux_clr; 18*d75b532aSSylvain Lemieux u32 p2_mux_state; 19*d75b532aSSylvain Lemieux u32 reserved2[51]; 20412ae53aSAlbert ARIBAUD \(3ADEV\) u32 p_mux_set; 21412ae53aSAlbert ARIBAUD \(3ADEV\) u32 p_mux_clr; 22412ae53aSAlbert ARIBAUD \(3ADEV\) u32 p_mux_state; 23*d75b532aSSylvain Lemieux u32 reserved3; 24*d75b532aSSylvain Lemieux u32 p3_mux_set; 25*d75b532aSSylvain Lemieux u32 p3_mux_clr; 26*d75b532aSSylvain Lemieux u32 p3_mux_state; 27*d75b532aSSylvain Lemieux u32 reserved4; 28*d75b532aSSylvain Lemieux u32 p0_mux_set; 29*d75b532aSSylvain Lemieux u32 p0_mux_clr; 30*d75b532aSSylvain Lemieux u32 p0_mux_state; 31*d75b532aSSylvain Lemieux u32 reserved5; 32*d75b532aSSylvain Lemieux u32 p1_mux_set; 33*d75b532aSSylvain Lemieux u32 p1_mux_clr; 34*d75b532aSSylvain Lemieux u32 p1_mux_state; 35412ae53aSAlbert ARIBAUD \(3ADEV\) }; 36