1*606f7047SAlbert ARIBAUD \(3ADEV\) /* 2*606f7047SAlbert ARIBAUD \(3ADEV\) * LPC32xx GPIO interface 3*606f7047SAlbert ARIBAUD \(3ADEV\) * 4*606f7047SAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2014 DENX Software Engineering GmbH 5*606f7047SAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6*606f7047SAlbert ARIBAUD \(3ADEV\) * 7*606f7047SAlbert ARIBAUD \(3ADEV\) * SPDX-License-Identifier: GPL-2.0+ 8*606f7047SAlbert ARIBAUD \(3ADEV\) */ 9*606f7047SAlbert ARIBAUD \(3ADEV\) 10*606f7047SAlbert ARIBAUD \(3ADEV\) /** 11*606f7047SAlbert ARIBAUD \(3ADEV\) * GPIO Register map for LPC32xx 12*606f7047SAlbert ARIBAUD \(3ADEV\) */ 13*606f7047SAlbert ARIBAUD \(3ADEV\) 14*606f7047SAlbert ARIBAUD \(3ADEV\) struct gpio_regs { 15*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p3_inp_state; 16*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p3_outp_set; 17*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p3_outp_clr; 18*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p3_outp_state; 19*606f7047SAlbert ARIBAUD \(3ADEV\) /* Watch out! the following are shared between p2 and p3 */ 20*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p2_p3_dir_set; 21*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p2_p3_dir_clr; 22*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p2_p3_dir_state; 23*606f7047SAlbert ARIBAUD \(3ADEV\) /* Now back to 'one register for one port' */ 24*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p2_inp_state; 25*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p2_outp_set; 26*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p2_outp_clr; 27*606f7047SAlbert ARIBAUD \(3ADEV\) u32 reserved1[6]; 28*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_inp_state; 29*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_outp_set; 30*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_outp_clr; 31*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_outp_state; 32*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_dir_set; 33*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_dir_clr; 34*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p0_dir_state; 35*606f7047SAlbert ARIBAUD \(3ADEV\) u32 reserved2; 36*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_inp_state; 37*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_outp_set; 38*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_outp_clr; 39*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_outp_state; 40*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_dir_set; 41*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_dir_clr; 42*606f7047SAlbert ARIBAUD \(3ADEV\) u32 p1_dir_state; 43*606f7047SAlbert ARIBAUD \(3ADEV\) }; 44