1*8a954eb6SPeter Griffin /* 2*8a954eb6SPeter Griffin * Copyright (C) 2015 Linaro 3*8a954eb6SPeter Griffin * Peter Griffin <peter.griffin@linaro.org> 4*8a954eb6SPeter Griffin * 5*8a954eb6SPeter Griffin * SPDX-License-Identifier: GPL-2.0+ 6*8a954eb6SPeter Griffin */ 7*8a954eb6SPeter Griffin 8*8a954eb6SPeter Griffin #ifndef __ASM_ARM_ARCH_PINMUX_H 9*8a954eb6SPeter Griffin #define __ASM_ARM_ARCH_PINMUX_H 10*8a954eb6SPeter Griffin 11*8a954eb6SPeter Griffin #include "periph.h" 12*8a954eb6SPeter Griffin 13*8a954eb6SPeter Griffin 14*8a954eb6SPeter Griffin /* iomg bit definition */ 15*8a954eb6SPeter Griffin #define MUX_M0 0 16*8a954eb6SPeter Griffin #define MUX_M1 1 17*8a954eb6SPeter Griffin #define MUX_M2 2 18*8a954eb6SPeter Griffin #define MUX_M3 3 19*8a954eb6SPeter Griffin #define MUX_M4 4 20*8a954eb6SPeter Griffin #define MUX_M5 5 21*8a954eb6SPeter Griffin #define MUX_M6 6 22*8a954eb6SPeter Griffin #define MUX_M7 7 23*8a954eb6SPeter Griffin 24*8a954eb6SPeter Griffin /* iocg bit definition */ 25*8a954eb6SPeter Griffin #define PULL_MASK (3) 26*8a954eb6SPeter Griffin #define PULL_DIS (0) 27*8a954eb6SPeter Griffin #define PULL_UP (1 << 0) 28*8a954eb6SPeter Griffin #define PULL_DOWN (1 << 1) 29*8a954eb6SPeter Griffin 30*8a954eb6SPeter Griffin /* drive strength definition */ 31*8a954eb6SPeter Griffin #define DRIVE_MASK (7 << 4) 32*8a954eb6SPeter Griffin #define DRIVE1_02MA (0 << 4) 33*8a954eb6SPeter Griffin #define DRIVE1_04MA (1 << 4) 34*8a954eb6SPeter Griffin #define DRIVE1_08MA (2 << 4) 35*8a954eb6SPeter Griffin #define DRIVE1_10MA (3 << 4) 36*8a954eb6SPeter Griffin #define DRIVE2_02MA (0 << 4) 37*8a954eb6SPeter Griffin #define DRIVE2_04MA (1 << 4) 38*8a954eb6SPeter Griffin #define DRIVE2_08MA (2 << 4) 39*8a954eb6SPeter Griffin #define DRIVE2_10MA (3 << 4) 40*8a954eb6SPeter Griffin #define DRIVE3_04MA (0 << 4) 41*8a954eb6SPeter Griffin #define DRIVE3_08MA (1 << 4) 42*8a954eb6SPeter Griffin #define DRIVE3_12MA (2 << 4) 43*8a954eb6SPeter Griffin #define DRIVE3_16MA (3 << 4) 44*8a954eb6SPeter Griffin #define DRIVE3_20MA (4 << 4) 45*8a954eb6SPeter Griffin #define DRIVE3_24MA (5 << 4) 46*8a954eb6SPeter Griffin #define DRIVE3_32MA (6 << 4) 47*8a954eb6SPeter Griffin #define DRIVE3_40MA (7 << 4) 48*8a954eb6SPeter Griffin #define DRIVE4_02MA (0 << 4) 49*8a954eb6SPeter Griffin #define DRIVE4_04MA (2 << 4) 50*8a954eb6SPeter Griffin #define DRIVE4_08MA (4 << 4) 51*8a954eb6SPeter Griffin #define DRIVE4_10MA (6 << 4) 52*8a954eb6SPeter Griffin 53*8a954eb6SPeter Griffin #define HI6220_PINMUX0_BASE 0xf7010000 54*8a954eb6SPeter Griffin #define HI6220_PINMUX1_BASE 0xf7010800 55*8a954eb6SPeter Griffin 56*8a954eb6SPeter Griffin #ifndef __ASSEMBLY__ 57*8a954eb6SPeter Griffin 58*8a954eb6SPeter Griffin /* maybe more registers, but highest used is 123 */ 59*8a954eb6SPeter Griffin #define REG_NUM 123 60*8a954eb6SPeter Griffin 61*8a954eb6SPeter Griffin struct hi6220_pinmux0_regs { 62*8a954eb6SPeter Griffin uint32_t iomg[REG_NUM]; 63*8a954eb6SPeter Griffin }; 64*8a954eb6SPeter Griffin 65*8a954eb6SPeter Griffin struct hi6220_pinmux1_regs { 66*8a954eb6SPeter Griffin uint32_t iocfg[REG_NUM]; 67*8a954eb6SPeter Griffin }; 68*8a954eb6SPeter Griffin 69*8a954eb6SPeter Griffin #endif 70*8a954eb6SPeter Griffin 71*8a954eb6SPeter Griffin /** 72*8a954eb6SPeter Griffin * Configures the pinmux for a particular peripheral. 73*8a954eb6SPeter Griffin * 74*8a954eb6SPeter Griffin * This function will configure the peripheral pinmux along with 75*8a954eb6SPeter Griffin * pull-up/down and drive strength. 76*8a954eb6SPeter Griffin * 77*8a954eb6SPeter Griffin * @param peripheral peripheral to be configured 78*8a954eb6SPeter Griffin * @return 0 if ok, -1 on error (e.g. unsupported peripheral) 79*8a954eb6SPeter Griffin */ 80*8a954eb6SPeter Griffin int hi6220_pinmux_config(int peripheral); 81*8a954eb6SPeter Griffin 82*8a954eb6SPeter Griffin #endif 83