1 /* 2 * (C) Copyright 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_WDT_H 8 #define _ASM_ARCH_WDT_H 9 10 #define WDT_BASE 0x1e785000 11 12 /* 13 * Special value that needs to be written to counter_restart register to 14 * (re)start the timer 15 */ 16 #define WDT_COUNTER_RESTART_VAL 0x4755 17 18 /* Control register */ 19 #define WDT_CTRL_RESET_MODE_SHIFT 5 20 #define WDT_CTRL_RESET_MODE_MASK 3 21 22 #define WDT_CTRL_EN (1 << 0) 23 #define WDT_CTRL_RESET (1 << 1) 24 #define WDT_CTRL_CLK1MHZ (1 << 4) 25 #define WDT_CTRL_2ND_BOOT (1 << 7) 26 27 /* Values for Reset Mode */ 28 #define WDT_CTRL_RESET_SOC 0 29 #define WDT_CTRL_RESET_CHIP 1 30 #define WDT_CTRL_RESET_CPU 2 31 #define WDT_CTRL_RESET_MASK 3 32 33 /* Reset Mask register */ 34 #define WDT_RESET_ARM (1 << 0) 35 #define WDT_RESET_COPROC (1 << 1) 36 #define WDT_RESET_SDRAM (1 << 2) 37 #define WDT_RESET_AHB (1 << 3) 38 #define WDT_RESET_I2C (1 << 4) 39 #define WDT_RESET_MAC1 (1 << 5) 40 #define WDT_RESET_MAC2 (1 << 6) 41 #define WDT_RESET_GCRT (1 << 7) 42 #define WDT_RESET_USB20 (1 << 8) 43 #define WDT_RESET_USB11_HOST (1 << 9) 44 #define WDT_RESET_USB11_EHCI2 (1 << 10) 45 #define WDT_RESET_VIDEO (1 << 11) 46 #define WDT_RESET_HAC (1 << 12) 47 #define WDT_RESET_LPC (1 << 13) 48 #define WDT_RESET_SDSDIO (1 << 14) 49 #define WDT_RESET_MIC (1 << 15) 50 #define WDT_RESET_CRT2C (1 << 16) 51 #define WDT_RESET_PWM (1 << 17) 52 #define WDT_RESET_PECI (1 << 18) 53 #define WDT_RESET_JTAG (1 << 19) 54 #define WDT_RESET_ADC (1 << 20) 55 #define WDT_RESET_GPIO (1 << 21) 56 #define WDT_RESET_MCTP (1 << 22) 57 #define WDT_RESET_XDMA (1 << 23) 58 #define WDT_RESET_SPI (1 << 24) 59 #define WDT_RESET_MISC (1 << 25) 60 61 #ifndef __ASSEMBLY__ 62 struct ast_wdt { 63 u32 counter_status; 64 u32 counter_reload_val; 65 u32 counter_restart; 66 u32 ctrl; 67 u32 timeout_status; 68 u32 clr_timeout_status; 69 u32 reset_width; 70 #ifdef CONFIG_ASPEED_AST2500 71 u32 reset_mask; 72 #else 73 u32 reserved0; 74 #endif 75 }; 76 77 void wdt_stop(struct ast_wdt *wdt); 78 void wdt_start(struct ast_wdt *wdt, u32 timeout); 79 80 /** 81 * Reset peripherals specified by mask 82 * 83 * Note, that this is only supported by ast2500 SoC 84 * 85 * @wdt: watchdog to use for this reset 86 * @mask: reset mask. 87 */ 88 int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask); 89 90 /** 91 * ast_get_wdt() - get a pointer to watchdog registers 92 * 93 * @wdt_number: 0-based WDT peripheral number 94 * @return pointer to registers or -ve error on error 95 */ 96 struct ast_wdt *ast_get_wdt(u8 wdt_number); 97 #endif /* __ASSEMBLY__ */ 98 99 #endif /* _ASM_ARCH_WDT_H */ 100