1*4697abeaSmaxims@google.com /* 2*4697abeaSmaxims@google.com * Copyright (c) 2016 Google, Inc 3*4697abeaSmaxims@google.com * 4*4697abeaSmaxims@google.com * SPDX-License-Identifier: GPL-2.0+ 5*4697abeaSmaxims@google.com */ 6*4697abeaSmaxims@google.com #ifndef _ASM_ARCH_TIMER_H 7*4697abeaSmaxims@google.com #define _ASM_ARCH_TIMER_H 8*4697abeaSmaxims@google.com 9*4697abeaSmaxims@google.com /* Each timer has 4 control bits in ctrl1 register. 10*4697abeaSmaxims@google.com * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, 11*4697abeaSmaxims@google.com * such that timer X uses bits (4 * X - 4):(4 * X - 1) 12*4697abeaSmaxims@google.com * If the timer does not support PWM, bit 4 is reserved. 13*4697abeaSmaxims@google.com */ 14*4697abeaSmaxims@google.com #define AST_TMC_EN (1 << 0) 15*4697abeaSmaxims@google.com #define AST_TMC_1MHZ (1 << 1) 16*4697abeaSmaxims@google.com #define AST_TMC_OVFINTR (1 << 2) 17*4697abeaSmaxims@google.com #define AST_TMC_PWM (1 << 3) 18*4697abeaSmaxims@google.com 19*4697abeaSmaxims@google.com /* Timers are counted from 1 in the datasheet. */ 20*4697abeaSmaxims@google.com #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) 21*4697abeaSmaxims@google.com 22*4697abeaSmaxims@google.com #define AST_TMC_RATE (1000*1000) 23*4697abeaSmaxims@google.com 24*4697abeaSmaxims@google.com #ifndef __ASSEMBLY__ 25*4697abeaSmaxims@google.com 26*4697abeaSmaxims@google.com /* 27*4697abeaSmaxims@google.com * All timers share control registers, which makes it harder to make them 28*4697abeaSmaxims@google.com * separate devices. Since only one timer is needed at the moment, making 29*4697abeaSmaxims@google.com * it this just one device. 30*4697abeaSmaxims@google.com */ 31*4697abeaSmaxims@google.com 32*4697abeaSmaxims@google.com struct ast_timer_counter { 33*4697abeaSmaxims@google.com u32 status; 34*4697abeaSmaxims@google.com u32 reload_val; 35*4697abeaSmaxims@google.com u32 match1; 36*4697abeaSmaxims@google.com u32 match2; 37*4697abeaSmaxims@google.com }; 38*4697abeaSmaxims@google.com 39*4697abeaSmaxims@google.com struct ast_timer { 40*4697abeaSmaxims@google.com struct ast_timer_counter timers1[3]; 41*4697abeaSmaxims@google.com u32 ctrl1; 42*4697abeaSmaxims@google.com u32 ctrl2; 43*4697abeaSmaxims@google.com #ifdef CONFIG_ASPEED_AST2500 44*4697abeaSmaxims@google.com u32 ctrl3; 45*4697abeaSmaxims@google.com u32 ctrl1_clr; 46*4697abeaSmaxims@google.com #else 47*4697abeaSmaxims@google.com u32 reserved[2]; 48*4697abeaSmaxims@google.com #endif 49*4697abeaSmaxims@google.com struct ast_timer_counter timers2[5]; 50*4697abeaSmaxims@google.com }; 51*4697abeaSmaxims@google.com 52*4697abeaSmaxims@google.com #endif /* __ASSEMBLY__ */ 53*4697abeaSmaxims@google.com 54*4697abeaSmaxims@google.com #endif /* _ASM_ARCH_TIMER_H */ 55