1732c7c24SAjay Bhargav /* 2732c7c24SAjay Bhargav * (C) Copyright 2012 3732c7c24SAjay Bhargav * eInfochips Ltd. <www.einfochips.com> 4*c7c47ca2SAjay Bhargav * Written-by: Ajay Bhargav <contact@8051projects.net> 5732c7c24SAjay Bhargav * 6732c7c24SAjay Bhargav * (C) Copyright 2009 7732c7c24SAjay Bhargav * Marvell Semiconductor <www.marvell.com> 8732c7c24SAjay Bhargav * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 10732c7c24SAjay Bhargav */ 11732c7c24SAjay Bhargav 12732c7c24SAjay Bhargav #ifndef __UTMI_ARMADA100__ 13732c7c24SAjay Bhargav #define __UTMI_ARMADA100__ 14732c7c24SAjay Bhargav 15732c7c24SAjay Bhargav #define UTMI_PHY_BASE 0xD4206000 16732c7c24SAjay Bhargav 17732c7c24SAjay Bhargav /* utmi_ctrl - bits */ 18732c7c24SAjay Bhargav #define INPKT_DELAY_SOF (1 << 28) 19732c7c24SAjay Bhargav #define PLL_PWR_UP 2 20732c7c24SAjay Bhargav #define PHY_PWR_UP 1 21732c7c24SAjay Bhargav 22732c7c24SAjay Bhargav /* utmi_pll - bits */ 23732c7c24SAjay Bhargav #define PLL_FBDIV_MASK 0x00000FF0 24732c7c24SAjay Bhargav #define PLL_FBDIV 4 25732c7c24SAjay Bhargav #define PLL_REFDIV_MASK 0x0000000F 26732c7c24SAjay Bhargav #define PLL_REFDIV 0 27732c7c24SAjay Bhargav #define PLL_READY 0x800000 28732c7c24SAjay Bhargav #define VCOCAL_START (1 << 21) 29732c7c24SAjay Bhargav 30732c7c24SAjay Bhargav #define N_DIVIDER 0xEE 31732c7c24SAjay Bhargav #define M_DIVIDER 0x0B 32732c7c24SAjay Bhargav 33732c7c24SAjay Bhargav /* utmi_tx - bits */ 34732c7c24SAjay Bhargav #define CK60_PHSEL 17 35732c7c24SAjay Bhargav #define PHSEL_VAL 0x4 36732c7c24SAjay Bhargav #define RCAL_START (1 << 12) 37732c7c24SAjay Bhargav 38732c7c24SAjay Bhargav /* 39732c7c24SAjay Bhargav * USB PHY registers 40732c7c24SAjay Bhargav * Refer Datasheet Appendix A.21 41732c7c24SAjay Bhargav */ 42732c7c24SAjay Bhargav struct armd1usb_phy_reg { 43732c7c24SAjay Bhargav u32 utmi_rev; /* USB PHY Revision */ 44732c7c24SAjay Bhargav u32 utmi_ctrl; /* USB PHY Control register */ 45732c7c24SAjay Bhargav u32 utmi_pll; /* PLL register */ 46732c7c24SAjay Bhargav u32 utmi_tx; /* Tx register */ 47732c7c24SAjay Bhargav u32 utmi_rx; /* Rx register */ 48732c7c24SAjay Bhargav u32 utmi_ivref; /* IVREF register */ 49732c7c24SAjay Bhargav u32 utmi_tst_g0; /* Test group 0 register */ 50732c7c24SAjay Bhargav u32 utmi_tst_g1; /* Test group 1 register */ 51732c7c24SAjay Bhargav u32 utmi_tst_g2; /* Test group 2 register */ 52732c7c24SAjay Bhargav u32 utmi_tst_g3; /* Test group 3 register */ 53732c7c24SAjay Bhargav u32 utmi_tst_g4; /* Test group 4 register */ 54732c7c24SAjay Bhargav u32 utmi_tst_g5; /* Test group 5 register */ 55732c7c24SAjay Bhargav u32 utmi_reserve; /* Reserve Register */ 56732c7c24SAjay Bhargav u32 utmi_usb_int; /* USB interuppt register */ 57732c7c24SAjay Bhargav u32 utmi_dbg_ctl; /* Debug control register */ 58732c7c24SAjay Bhargav u32 utmi_otg_addon; /* OTG addon register */ 59732c7c24SAjay Bhargav }; 60732c7c24SAjay Bhargav 61732c7c24SAjay Bhargav int utmi_init(void); 62732c7c24SAjay Bhargav 63732c7c24SAjay Bhargav #endif /* __UTMI_ARMADA100__ */ 64