13cf97f45SAjay Bhargav /* 23cf97f45SAjay Bhargav * (C) Copyright 2011 33cf97f45SAjay Bhargav * eInfochips Ltd. <www.einfochips.com> 4*c7c47ca2SAjay Bhargav * Written-by: Ajay Bhargav <contact@8051projects.net> 53cf97f45SAjay Bhargav * 63cf97f45SAjay Bhargav * (C) Copyright 2010 73cf97f45SAjay Bhargav * Marvell Semiconductor <www.marvell.com> 83cf97f45SAjay Bhargav * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 103cf97f45SAjay Bhargav */ 113cf97f45SAjay Bhargav 123cf97f45SAjay Bhargav #ifndef _ASM_ARCH_GPIO_H 133cf97f45SAjay Bhargav #define _ASM_ARCH_GPIO_H 143cf97f45SAjay Bhargav 153cf97f45SAjay Bhargav #include <asm/types.h> 163cf97f45SAjay Bhargav #include <asm/arch/armada100.h> 173cf97f45SAjay Bhargav 183cf97f45SAjay Bhargav #define GPIO_HIGH 1 193cf97f45SAjay Bhargav #define GPIO_LOW 0 203cf97f45SAjay Bhargav 213cf97f45SAjay Bhargav #define GPIO_TO_REG(gp) (gp >> 5) 223cf97f45SAjay Bhargav #define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) 233cf97f45SAjay Bhargav #define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) 243cf97f45SAjay Bhargav get_gpio_base(int bank)253cf97f45SAjay Bhargavstatic inline void *get_gpio_base(int bank) 263cf97f45SAjay Bhargav { 273cf97f45SAjay Bhargav const unsigned int offset[4] = {0, 4, 8, 0x100}; 283cf97f45SAjay Bhargav /* gpio register bank offset - refer Appendix A.36 */ 293cf97f45SAjay Bhargav return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); 303cf97f45SAjay Bhargav } 313cf97f45SAjay Bhargav 323cf97f45SAjay Bhargav #endif /* _ASM_ARCH_GPIO_H */ 33