1*6c08d5dcSPrafulla Wadaskar /* 2*6c08d5dcSPrafulla Wadaskar * (C) Copyright 2010 3*6c08d5dcSPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 4*6c08d5dcSPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com> 5*6c08d5dcSPrafulla Wadaskar * 6*6c08d5dcSPrafulla Wadaskar * See file CREDITS for list of people who contributed to this 7*6c08d5dcSPrafulla Wadaskar * project. 8*6c08d5dcSPrafulla Wadaskar * 9*6c08d5dcSPrafulla Wadaskar * This program is free software; you can redistribute it and/or 10*6c08d5dcSPrafulla Wadaskar * modify it under the terms of the GNU General Public License as 11*6c08d5dcSPrafulla Wadaskar * published by the Free Software Foundation; either version 2 of 12*6c08d5dcSPrafulla Wadaskar * the License, or (at your option) any later version. 13*6c08d5dcSPrafulla Wadaskar * 14*6c08d5dcSPrafulla Wadaskar * This program is distributed in the hope that it will be useful, 15*6c08d5dcSPrafulla Wadaskar * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*6c08d5dcSPrafulla Wadaskar * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*6c08d5dcSPrafulla Wadaskar * GNU General Public License for more details. 18*6c08d5dcSPrafulla Wadaskar * 19*6c08d5dcSPrafulla Wadaskar * You should have received a copy of the GNU General Public License 20*6c08d5dcSPrafulla Wadaskar * along with this program; if not, write to the Free Software 21*6c08d5dcSPrafulla Wadaskar * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22*6c08d5dcSPrafulla Wadaskar * MA 02110-1301 USA 23*6c08d5dcSPrafulla Wadaskar */ 24*6c08d5dcSPrafulla Wadaskar 25*6c08d5dcSPrafulla Wadaskar #ifndef _ARMADA100CPU_H 26*6c08d5dcSPrafulla Wadaskar #define _ARMADA100CPU_H 27*6c08d5dcSPrafulla Wadaskar 28*6c08d5dcSPrafulla Wadaskar #include <asm/io.h> 29*6c08d5dcSPrafulla Wadaskar #include <asm/system.h> 30*6c08d5dcSPrafulla Wadaskar 31*6c08d5dcSPrafulla Wadaskar /* 32*6c08d5dcSPrafulla Wadaskar * CPU Interface Registers 33*6c08d5dcSPrafulla Wadaskar * Refer Datasheet Appendix A.2 34*6c08d5dcSPrafulla Wadaskar */ 35*6c08d5dcSPrafulla Wadaskar struct armd1cpu_registers { 36*6c08d5dcSPrafulla Wadaskar u32 chip_id; /* Chip Id Reg */ 37*6c08d5dcSPrafulla Wadaskar u32 pad; 38*6c08d5dcSPrafulla Wadaskar u32 cpu_conf; /* CPU Conf Reg */ 39*6c08d5dcSPrafulla Wadaskar u32 pad1; 40*6c08d5dcSPrafulla Wadaskar u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ 41*6c08d5dcSPrafulla Wadaskar u32 pad2; 42*6c08d5dcSPrafulla Wadaskar u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ 43*6c08d5dcSPrafulla Wadaskar u32 mcb_conf; /* MCB Conf Reg */ 44*6c08d5dcSPrafulla Wadaskar u32 sys_boot_ctl; /* Sytem Boot Control */ 45*6c08d5dcSPrafulla Wadaskar }; 46*6c08d5dcSPrafulla Wadaskar 47*6c08d5dcSPrafulla Wadaskar /* 48*6c08d5dcSPrafulla Wadaskar * Functions 49*6c08d5dcSPrafulla Wadaskar */ 50*6c08d5dcSPrafulla Wadaskar u32 armd1_sdram_base(int); 51*6c08d5dcSPrafulla Wadaskar u32 armd1_sdram_size(int); 52*6c08d5dcSPrafulla Wadaskar 53*6c08d5dcSPrafulla Wadaskar #endif /* _ARMADA100CPU_H */ 54