16c08d5dcSPrafulla Wadaskar /* 26c08d5dcSPrafulla Wadaskar * (C) Copyright 2010 36c08d5dcSPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 46c08d5dcSPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 56c08d5dcSPrafulla Wadaskar * Contributor: Mahavir Jain <mjain@marvell.com> 66c08d5dcSPrafulla Wadaskar * 7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 86c08d5dcSPrafulla Wadaskar */ 96c08d5dcSPrafulla Wadaskar 106c08d5dcSPrafulla Wadaskar #ifndef _ASM_ARCH_ARMADA100_H 116c08d5dcSPrafulla Wadaskar #define _ASM_ARCH_ARMADA100_H 126c08d5dcSPrafulla Wadaskar 136c08d5dcSPrafulla Wadaskar #if defined (CONFIG_ARMADA100) 146c08d5dcSPrafulla Wadaskar 156c08d5dcSPrafulla Wadaskar /* Common APB clock register bit definitions */ 166c08d5dcSPrafulla Wadaskar #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ 176c08d5dcSPrafulla Wadaskar #define APBC_FNCLK (1<<1) /* Functional Clock Enable */ 186c08d5dcSPrafulla Wadaskar #define APBC_RST (1<<2) /* Reset Generation */ 196c08d5dcSPrafulla Wadaskar /* Functional Clock Selection Mask */ 206c08d5dcSPrafulla Wadaskar #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) 216c08d5dcSPrafulla Wadaskar 22aa0ecfebSAjay Bhargav /* Fast Ethernet Controller Clock register definition */ 23aa0ecfebSAjay Bhargav #define FE_CLK_RST 0x1 24aa0ecfebSAjay Bhargav #define FE_CLK_ENA 0x8 25aa0ecfebSAjay Bhargav 26daa4b2f7SAjay Bhargav /* SSP2 Clock Control */ 27daa4b2f7SAjay Bhargav #define SSP2_APBCLK 0x01 28daa4b2f7SAjay Bhargav #define SSP2_FNCLK 0x02 29daa4b2f7SAjay Bhargav 30732c7c24SAjay Bhargav /* USB Clock/reset control bits */ 31732c7c24SAjay Bhargav #define USB_SPH_AXICLK_EN 0x10 32732c7c24SAjay Bhargav #define USB_SPH_AXI_RST 0x02 33732c7c24SAjay Bhargav 34732c7c24SAjay Bhargav /* MPMU Clocks */ 35732c7c24SAjay Bhargav #define APB2_26M_EN (1 << 20) 36732c7c24SAjay Bhargav #define AP_26M (1 << 4) 37732c7c24SAjay Bhargav 386c08d5dcSPrafulla Wadaskar /* Register Base Addresses */ 396c08d5dcSPrafulla Wadaskar #define ARMD1_DRAM_BASE 0xB0000000 4079788bb1SAjay Bhargav #define ARMD1_FEC_BASE 0xC0800000 416c08d5dcSPrafulla Wadaskar #define ARMD1_TIMER_BASE 0xD4014000 426c08d5dcSPrafulla Wadaskar #define ARMD1_APBC1_BASE 0xD4015000 436c08d5dcSPrafulla Wadaskar #define ARMD1_APBC2_BASE 0xD4015800 446c08d5dcSPrafulla Wadaskar #define ARMD1_UART1_BASE 0xD4017000 456c08d5dcSPrafulla Wadaskar #define ARMD1_UART2_BASE 0xD4018000 466c08d5dcSPrafulla Wadaskar #define ARMD1_GPIO_BASE 0xD4019000 476c08d5dcSPrafulla Wadaskar #define ARMD1_SSP1_BASE 0xD401B000 486c08d5dcSPrafulla Wadaskar #define ARMD1_SSP2_BASE 0xD401C000 496c08d5dcSPrafulla Wadaskar #define ARMD1_MFPR_BASE 0xD401E000 506c08d5dcSPrafulla Wadaskar #define ARMD1_SSP3_BASE 0xD401F000 516c08d5dcSPrafulla Wadaskar #define ARMD1_SSP4_BASE 0xD4020000 526c08d5dcSPrafulla Wadaskar #define ARMD1_SSP5_BASE 0xD4021000 536c08d5dcSPrafulla Wadaskar #define ARMD1_UART3_BASE 0xD4026000 546c08d5dcSPrafulla Wadaskar #define ARMD1_MPMU_BASE 0xD4050000 5554cb0048SAjay Bhargav #define ARMD1_USB_HOST_BASE 0xD4209000 566c08d5dcSPrafulla Wadaskar #define ARMD1_APMU_BASE 0xD4282800 576c08d5dcSPrafulla Wadaskar #define ARMD1_CPU_BASE 0xD4282C00 586c08d5dcSPrafulla Wadaskar 596c08d5dcSPrafulla Wadaskar #endif /* CONFIG_ARMADA100 */ 606c08d5dcSPrafulla Wadaskar #endif /* _ASM_ARCH_ARMADA100_H */ 61