162d7fe7cSChandan Nath /* 262d7fe7cSChandan Nath * sys_proto.h 362d7fe7cSChandan Nath * 462d7fe7cSChandan Nath * System information header 562d7fe7cSChandan Nath * 662d7fe7cSChandan Nath * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 762d7fe7cSChandan Nath * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 962d7fe7cSChandan Nath */ 1062d7fe7cSChandan Nath 1162d7fe7cSChandan Nath #ifndef _SYS_PROTO_H_ 1262d7fe7cSChandan Nath #define _SYS_PROTO_H_ 1362d7fe7cSChandan Nath 1462d7fe7cSChandan Nath #define BOARD_REV_ID 0x0 1562d7fe7cSChandan Nath 1662d7fe7cSChandan Nath u32 get_cpu_rev(void); 1762d7fe7cSChandan Nath u32 get_sysboot_value(void); 1862d7fe7cSChandan Nath 1962d7fe7cSChandan Nath #ifdef CONFIG_DISPLAY_CPUINFO 2062d7fe7cSChandan Nath int print_cpuinfo(void); 2162d7fe7cSChandan Nath #endif 2262d7fe7cSChandan Nath 236995a289SSatyanarayana, Sandhya extern struct ctrl_stat *cstat; 2462d7fe7cSChandan Nath u32 get_device_type(void); 254596dcc1STom Rini void save_omap_boot_params(void); 268a8f084eSChandan Nath void setup_clocks_for_console(void); 277b9c5d0bSHeiko Schocher void mpu_pll_config_val(int mpull_m); 28b971dfadSTom Rini void ddr_pll_config(unsigned int ddrpll_M); 29db7dd810STom Rini 308eb16b7fSIlya Yanok void sdelay(unsigned long); 3198f92001STom Rini 3298f92001STom Rini struct gpmc_cs; 338eb16b7fSIlya Yanok void gpmc_init(void); 346b3dcc45SMark Jackson void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, 356b3dcc45SMark Jackson u32 size); 36da634ae3SAndreas Bießmann void omap_nand_switch_ecc(uint32_t, uint32_t); 3749f78365SHeiko Schocher 3849f78365SHeiko Schocher void rtc32k_enable(void); 397ea7f689SHeiko Schocher void uart_soft_reset(void); 40*94d77fb6SLokesh Vutla u32 wait_on_value(u32, u32, void *, u32); 4162d7fe7cSChandan Nath #endif 42