1b43c17cbSMatt Porter /* 2b43c17cbSMatt Porter * hardware_ti814x.h 3b43c17cbSMatt Porter * 4b43c17cbSMatt Porter * TI814x hardware specific header 5b43c17cbSMatt Porter * 6b43c17cbSMatt Porter * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7b43c17cbSMatt Porter * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9b43c17cbSMatt Porter */ 10b43c17cbSMatt Porter 11b43c17cbSMatt Porter #ifndef __AM33XX_HARDWARE_TI814X_H 12b43c17cbSMatt Porter #define __AM33XX_HARDWARE_TI814X_H 13b43c17cbSMatt Porter 148b029f22SMatt Porter /* Module base addresses */ 158b029f22SMatt Porter 168b029f22SMatt Porter /* UART Base Address */ 178b029f22SMatt Porter #define UART0_BASE 0x48020000 188b029f22SMatt Porter 198b029f22SMatt Porter /* Watchdog Timer */ 208b029f22SMatt Porter #define WDT_BASE 0x481C7000 218b029f22SMatt Porter 228b029f22SMatt Porter /* Control Module Base Address */ 238b029f22SMatt Porter #define CTRL_BASE 0x48140000 24035d5639SMatt Porter #define CTRL_DEVICE_BASE 0x48140600 258b029f22SMatt Porter 268b029f22SMatt Porter /* PRCM Base Address */ 278b029f22SMatt Porter #define PRCM_BASE 0x48180000 28c06e498aSLokesh Vutla #define CM_PER 0x44E00000 29c06e498aSLokesh Vutla #define CM_WKUP 0x44E00400 30c06e498aSLokesh Vutla 31c06e498aSLokesh Vutla #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 32c06e498aSLokesh Vutla #define PRM_RSTST (PRM_RSTCTRL + 8) 338b029f22SMatt Porter 348b029f22SMatt Porter /* PLL Subsystem Base Address */ 358b029f22SMatt Porter #define PLL_SUBSYS_BASE 0x481C5000 368b029f22SMatt Porter 37b43c17cbSMatt Porter /* VTP Base address */ 38b43c17cbSMatt Porter #define VTP0_CTRL_ADDR 0x48140E0C 39*dcf846d5STENART Antoine #define VTP1_CTRL_ADDR 0x48140E10 40b43c17cbSMatt Porter 41b43c17cbSMatt Porter /* DDR Base address */ 42b43c17cbSMatt Porter #define DDR_PHY_CMD_ADDR 0x47C0C400 43b43c17cbSMatt Porter #define DDR_PHY_DATA_ADDR 0x47C0C4C8 44*dcf846d5STENART Antoine #define DDR_PHY_CMD_ADDR2 0x47C0C800 45*dcf846d5STENART Antoine #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 46b43c17cbSMatt Porter #define DDR_DATA_REGS_NR 4 47b43c17cbSMatt Porter 48*dcf846d5STENART Antoine #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 49*dcf846d5STENART Antoine #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 50*dcf846d5STENART Antoine 518b029f22SMatt Porter /* CPSW Config space */ 528b029f22SMatt Porter #define CPSW_MDIO_BASE 0x4A100800 538b029f22SMatt Porter 548b029f22SMatt Porter /* RTC base address */ 558b029f22SMatt Porter #define RTC_BASE 0x480C0000 568b029f22SMatt Porter 57c06e498aSLokesh Vutla /* OTG */ 58c06e498aSLokesh Vutla #define USB0_OTG_BASE 0x47401000 59c06e498aSLokesh Vutla #define USB1_OTG_BASE 0x47401800 60c06e498aSLokesh Vutla 61b43c17cbSMatt Porter #endif /* __AM33XX_HARDWARE_TI814X_H */ 62