1c06e498aSLokesh Vutla /* 2c06e498aSLokesh Vutla * hardware_am43xx.h 3c06e498aSLokesh Vutla * 4c06e498aSLokesh Vutla * AM43xx hardware specific header 5c06e498aSLokesh Vutla * 6c06e498aSLokesh Vutla * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7c06e498aSLokesh Vutla * 8c06e498aSLokesh Vutla * SPDX-License-Identifier: GPL-2.0+ 9c06e498aSLokesh Vutla */ 10c06e498aSLokesh Vutla 11c06e498aSLokesh Vutla #ifndef __AM43XX_HARDWARE_AM43XX_H 12c06e498aSLokesh Vutla #define __AM43XX_HARDWARE_AM43XX_H 13c06e498aSLokesh Vutla 14c06e498aSLokesh Vutla /* Module base addresses */ 15c06e498aSLokesh Vutla 168038b497SCooper Jr., Franklin /* L3 Fast Configuration Bandwidth Limiter Base Address */ 178038b497SCooper Jr., Franklin #define L3F_CFG_BWLIMITER 0x44005200 188038b497SCooper Jr., Franklin 19c06e498aSLokesh Vutla /* UART Base Address */ 20c06e498aSLokesh Vutla #define UART0_BASE 0x44E09000 21c06e498aSLokesh Vutla 22c06e498aSLokesh Vutla /* GPIO Base address */ 23c06e498aSLokesh Vutla #define GPIO2_BASE 0x481AC000 24c06e498aSLokesh Vutla 25c06e498aSLokesh Vutla /* Watchdog Timer */ 26c06e498aSLokesh Vutla #define WDT_BASE 0x44E35000 27c06e498aSLokesh Vutla 28c06e498aSLokesh Vutla /* Control Module Base Address */ 29c06e498aSLokesh Vutla #define CTRL_BASE 0x44E10000 30c06e498aSLokesh Vutla #define CTRL_DEVICE_BASE 0x44E10600 31c06e498aSLokesh Vutla 32c06e498aSLokesh Vutla /* PRCM Base Address */ 33c06e498aSLokesh Vutla #define PRCM_BASE 0x44DF0000 34c06e498aSLokesh Vutla #define CM_WKUP 0x44DF2800 35c06e498aSLokesh Vutla #define CM_PER 0x44DF8800 367ca1b2a2SLokesh Vutla #define CM_DPLL 0x44DF4200 377ca1b2a2SLokesh Vutla #define CM_RTC 0x44DF8500 38c06e498aSLokesh Vutla 39c06e498aSLokesh Vutla #define PRM_RSTCTRL (PRCM_BASE + 0x4000) 40c06e498aSLokesh Vutla #define PRM_RSTST (PRM_RSTCTRL + 4) 41c06e498aSLokesh Vutla 42c06e498aSLokesh Vutla /* VTP Base address */ 43c06e498aSLokesh Vutla #define VTP0_CTRL_ADDR 0x44E10E0C 44dcf846d5STENART Antoine #define VTP1_CTRL_ADDR 0x48140E10 45c06e498aSLokesh Vutla 465ba95541SFelipe Balbi /* USB CTRL Base Address */ 475ba95541SFelipe Balbi #define USB1_CTRL 0x44e10628 485ba95541SFelipe Balbi #define USB1_CTRL_CM_PWRDN BIT(0) 495ba95541SFelipe Balbi #define USB1_CTRL_OTG_PWRDN BIT(1) 505ba95541SFelipe Balbi 51c06e498aSLokesh Vutla /* DDR Base address */ 52c06e498aSLokesh Vutla #define DDR_PHY_CMD_ADDR 0x44E12000 53c06e498aSLokesh Vutla #define DDR_PHY_DATA_ADDR 0x44E120C8 54dcf846d5STENART Antoine #define DDR_PHY_CMD_ADDR2 0x47C0C800 55dcf846d5STENART Antoine #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 56c06e498aSLokesh Vutla #define DDR_DATA_REGS_NR 2 57c06e498aSLokesh Vutla 58c06e498aSLokesh Vutla /* CPSW Config space */ 59c06e498aSLokesh Vutla #define CPSW_MDIO_BASE 0x4A101000 60c06e498aSLokesh Vutla 61c06e498aSLokesh Vutla /* RTC base address */ 62c06e498aSLokesh Vutla #define RTC_BASE 0x44E3E000 63c06e498aSLokesh Vutla 649f81eb77SKishon Vijay Abraham I /* USB OTG */ 659f81eb77SKishon Vijay Abraham I #define USB_OTG_SS1_BASE 0x48390000 669f81eb77SKishon Vijay Abraham I #define USB_OTG_SS1_GLUE_BASE 0x48380000 679f81eb77SKishon Vijay Abraham I #define USB2_PHY1_POWER 0x44E10620 689f81eb77SKishon Vijay Abraham I 699f81eb77SKishon Vijay Abraham I #define USB_OTG_SS2_BASE 0x483D0000 709f81eb77SKishon Vijay Abraham I #define USB_OTG_SS2_GLUE_BASE 0x483C0000 719f81eb77SKishon Vijay Abraham I #define USB2_PHY2_POWER 0x44E10628 729f81eb77SKishon Vijay Abraham I 733d799c7fSDan Murphy /* USB Clock Control */ 743d799c7fSDan Murphy #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) 753d799c7fSDan Murphy #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) 76052fb196SDan Murphy #define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) 773d799c7fSDan Murphy #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 783d799c7fSDan Murphy 793d799c7fSDan Murphy #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) 803d799c7fSDan Murphy #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) 81052fb196SDan Murphy #define USBPHYOCPSCP_MODULE_EN (1 << 1) 82d3daba10SLokesh Vutla #define CM_DEVICE_INST 0x44df4100 83fc46bae2SJames Doublesin #define PRM_DEVICE_INST 0x44df4000 843d799c7fSDan Murphy 85fc2f15d2SKishon Vijay Abraham I #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 86fc2f15d2SKishon Vijay Abraham I #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 87fc2f15d2SKishon Vijay Abraham I 88*2d134597SVignesh R /* EDMA3 Base Address */ 89*2d134597SVignesh R #define EDMA3_BASE 0x49000000 90*2d134597SVignesh R 91c06e498aSLokesh Vutla #endif /* __AM43XX_HARDWARE_AM43XX_H */ 92