1b43c17cbSMatt Porter /* 2b43c17cbSMatt Porter * hardware_am33xx.h 3b43c17cbSMatt Porter * 4b43c17cbSMatt Porter * AM33xx hardware specific header 5b43c17cbSMatt Porter * 6b43c17cbSMatt Porter * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7b43c17cbSMatt Porter * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9b43c17cbSMatt Porter */ 10b43c17cbSMatt Porter 11b43c17cbSMatt Porter #ifndef __AM33XX_HARDWARE_AM33XX_H 12b43c17cbSMatt Porter #define __AM33XX_HARDWARE_AM33XX_H 13b43c17cbSMatt Porter 148b029f22SMatt Porter /* Module base addresses */ 158b029f22SMatt Porter 168b029f22SMatt Porter /* UART Base Address */ 178b029f22SMatt Porter #define UART0_BASE 0x44E09000 188b029f22SMatt Porter 198b029f22SMatt Porter /* GPIO Base address */ 208b029f22SMatt Porter #define GPIO2_BASE 0x481AC000 218b029f22SMatt Porter 228b029f22SMatt Porter /* Watchdog Timer */ 238b029f22SMatt Porter #define WDT_BASE 0x44E35000 248b029f22SMatt Porter 258b029f22SMatt Porter /* Control Module Base Address */ 268b029f22SMatt Porter #define CTRL_BASE 0x44E10000 278b029f22SMatt Porter #define CTRL_DEVICE_BASE 0x44E10600 288b029f22SMatt Porter 298b029f22SMatt Porter /* PRCM Base Address */ 308b029f22SMatt Porter #define PRCM_BASE 0x44E00000 31c06e498aSLokesh Vutla #define CM_PER 0x44E00000 32c06e498aSLokesh Vutla #define CM_WKUP 0x44E00400 337ca1b2a2SLokesh Vutla #define CM_DPLL 0x44E00500 347ca1b2a2SLokesh Vutla #define CM_RTC 0x44E00800 35c06e498aSLokesh Vutla 36c06e498aSLokesh Vutla #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) 37c06e498aSLokesh Vutla #define PRM_RSTST (PRM_RSTCTRL + 8) 388b029f22SMatt Porter 39b43c17cbSMatt Porter /* VTP Base address */ 40b43c17cbSMatt Porter #define VTP0_CTRL_ADDR 0x44E10E0C 41dcf846d5STENART Antoine #define VTP1_CTRL_ADDR 0x48140E10 42fc46bae2SJames Doublesin #define PRM_DEVICE_INST 0x44E00F00 43b43c17cbSMatt Porter 44b43c17cbSMatt Porter /* DDR Base address */ 45b43c17cbSMatt Porter #define DDR_PHY_CMD_ADDR 0x44E12000 46b43c17cbSMatt Porter #define DDR_PHY_DATA_ADDR 0x44E120C8 47dcf846d5STENART Antoine #define DDR_PHY_CMD_ADDR2 0x47C0C800 48dcf846d5STENART Antoine #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 49b43c17cbSMatt Porter #define DDR_DATA_REGS_NR 2 50b43c17cbSMatt Porter 51dcf846d5STENART Antoine #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 52dcf846d5STENART Antoine #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 53dcf846d5STENART Antoine 548b029f22SMatt Porter /* CPSW Config space */ 558b029f22SMatt Porter #define CPSW_MDIO_BASE 0x4A101000 568b029f22SMatt Porter 578b029f22SMatt Porter /* RTC base address */ 588b029f22SMatt Porter #define RTC_BASE 0x44E3E000 598b029f22SMatt Porter 60c06e498aSLokesh Vutla /* OTG */ 61c06e498aSLokesh Vutla #define USB0_OTG_BASE 0x47401000 62c06e498aSLokesh Vutla #define USB1_OTG_BASE 0x47401800 63c06e498aSLokesh Vutla 6414c0158bSHeiko Schocher /* LCD Controller */ 6514c0158bSHeiko Schocher #define LCD_CNTL_BASE 0x4830E000 6614c0158bSHeiko Schocher 6714c0158bSHeiko Schocher /* PWMSS */ 6814c0158bSHeiko Schocher #define PWMSS0_BASE 0x48300000 6914c0158bSHeiko Schocher #define AM33XX_ECAP0_BASE 0x48300100 70*f61c9bcdStomas.melin@vaisala.com #define AM33XX_EPWM_BASE 0x48300200 7114c0158bSHeiko Schocher 72b43c17cbSMatt Porter #endif /* __AM33XX_HARDWARE_AM33XX_H */ 73