15655108aSChandan Nath /* 25655108aSChandan Nath * hardware.h 35655108aSChandan Nath * 45655108aSChandan Nath * hardware specific header 55655108aSChandan Nath * 63ba65f97SMatt Porter * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 75655108aSChandan Nath * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 95655108aSChandan Nath */ 105655108aSChandan Nath 115655108aSChandan Nath #ifndef __AM33XX_HARDWARE_H 125655108aSChandan Nath #define __AM33XX_HARDWARE_H 135655108aSChandan Nath 148b029f22SMatt Porter #include <config.h> 1541aebf81STom Rini #include <asm/arch/omap.h> 163ba65f97SMatt Porter #ifdef CONFIG_AM33XX 173ba65f97SMatt Porter #include <asm/arch/hardware_am33xx.h> 18dcf846d5STENART Antoine #elif defined(CONFIG_TI816X) 19dcf846d5STENART Antoine #include <asm/arch/hardware_ti816x.h> 203ba65f97SMatt Porter #elif defined(CONFIG_TI814X) 213ba65f97SMatt Porter #include <asm/arch/hardware_ti814x.h> 22c06e498aSLokesh Vutla #elif defined(CONFIG_AM43XX) 23c06e498aSLokesh Vutla #include <asm/arch/hardware_am43xx.h> 243ba65f97SMatt Porter #endif 2541aebf81STom Rini 268b029f22SMatt Porter /* 278b029f22SMatt Porter * Common hardware definitions 288b029f22SMatt Porter */ 295655108aSChandan Nath 305655108aSChandan Nath /* DM Timer base addresses */ 315655108aSChandan Nath #define DM_TIMER0_BASE 0x4802C000 325655108aSChandan Nath #define DM_TIMER1_BASE 0x4802E000 335655108aSChandan Nath #define DM_TIMER2_BASE 0x48040000 345655108aSChandan Nath #define DM_TIMER3_BASE 0x48042000 355655108aSChandan Nath #define DM_TIMER4_BASE 0x48044000 365655108aSChandan Nath #define DM_TIMER5_BASE 0x48046000 375655108aSChandan Nath #define DM_TIMER6_BASE 0x48048000 385655108aSChandan Nath #define DM_TIMER7_BASE 0x4804A000 395655108aSChandan Nath 405655108aSChandan Nath /* GPIO Base address */ 415655108aSChandan Nath #define GPIO0_BASE 0x48032000 425655108aSChandan Nath #define GPIO1_BASE 0x4804C000 435655108aSChandan Nath 445655108aSChandan Nath /* BCH Error Location Module */ 455655108aSChandan Nath #define ELM_BASE 0x48080000 465655108aSChandan Nath 475655108aSChandan Nath /* EMIF Base address */ 485655108aSChandan Nath #define EMIF4_0_CFG_BASE 0x4C000000 495655108aSChandan Nath #define EMIF4_1_CFG_BASE 0x4D000000 505655108aSChandan Nath 515655108aSChandan Nath /* DDR Base address */ 525655108aSChandan Nath #define DDR_CTRL_ADDR 0x44E10E04 535655108aSChandan Nath #define DDR_CONTROL_BASE_ADDR 0x44E11404 545655108aSChandan Nath 555655108aSChandan Nath /* UART */ 565655108aSChandan Nath #define DEFAULT_UART_BASE UART0_BASE 575655108aSChandan Nath 588eb16b7fSIlya Yanok /* GPMC Base address */ 598eb16b7fSIlya Yanok #define GPMC_BASE 0x50000000 608eb16b7fSIlya Yanok 61e79cd8ebSChandan Nath /* CPSW Config space */ 6281df2babSMatt Porter #define CPSW_BASE 0x4A100000 63000820b5SVaibhav Hiremath 64*fbd6295dSLokesh Vutla /* Control status register */ 65*fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) 66*fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 67*fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) 68*fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 69*fbd6295dSLokesh Vutla #define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) 70*fbd6295dSLokesh Vutla #define CTRL_SYSBOOT_15_14_SHIFT 22 71*fbd6295dSLokesh Vutla 72*fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 73*fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 74*fbd6295dSLokesh Vutla 75*fbd6295dSLokesh Vutla #define NUM_CRYSTAL_FREQ 0x4 76*fbd6295dSLokesh Vutla 77b424aae4SHeiko Schocher int clk_get(int clk); 785655108aSChandan Nath #endif /* __AM33XX_HARDWARE_H */ 79