1 /* 2 * ddr_defs.h 3 * 4 * ddr specific header 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _DDR_DEFS_H 20 #define _DDR_DEFS_H 21 22 #include <asm/arch/hardware.h> 23 24 /* AM335X EMIF Register values */ 25 #define VTP_CTRL_READY (0x1 << 5) 26 #define VTP_CTRL_ENABLE (0x1 << 6) 27 #define VTP_CTRL_START_EN (0x1) 28 #define CMD_FORCE 0x00 29 #define CMD_DELAY 0x00 30 #define PHY_DLL_LOCK_DIFF 0x0 31 32 #define DDR2_EMIF_READ_LATENCY 0x05 33 #define DDR2_EMIF_TIM1 0x0666B3D6 34 #define DDR2_EMIF_TIM2 0x143731DA 35 #define DDR2_EMIF_TIM3 0x00000347 36 #define DDR2_EMIF_SDCFG 0x43805332 37 #define DDR2_EMIF_SDREF 0x0000081a 38 #define DDR2_DLL_LOCK_DIFF 0x0 39 #define DDR2_RATIO 0x80 40 #define DDR2_INVERT_CLKOUT 0x00 41 #define DDR2_RD_DQS 0x12 42 #define DDR2_WR_DQS 0x00 43 #define DDR2_PHY_WRLVL 0x00 44 #define DDR2_PHY_GATELVL 0x00 45 #define DDR2_PHY_WR_DATA 0x40 46 #define DDR2_PHY_FIFO_WE 0x80 47 #define DDR2_PHY_RANK0_DELAY 0x1 48 #define DDR2_IOCTRL_VALUE 0x18B 49 50 /** 51 * Encapsulates DDR PHY control and corresponding shadow registers. 52 */ 53 struct ddr_phy_control { 54 unsigned long reg; 55 unsigned long reg_sh; 56 unsigned long reg2; 57 }; 58 59 /** 60 * Encapsulates SDRAM timing and corresponding shadow registers. 61 */ 62 struct sdram_timing { 63 unsigned long time1; 64 unsigned long time1_sh; 65 unsigned long time2; 66 unsigned long time2_sh; 67 unsigned long time3; 68 unsigned long time3_sh; 69 }; 70 71 /** 72 * Encapsulates SDRAM configuration. 73 * (Includes refresh control registers) */ 74 struct sdram_config { 75 unsigned long sdrcr; 76 unsigned long sdrcr2; 77 unsigned long refresh; 78 unsigned long refresh_sh; 79 }; 80 81 /** 82 * Configure SDRAM 83 */ 84 int config_sdram(struct sdram_config *cfg); 85 86 /** 87 * Set SDRAM timings 88 */ 89 int set_sdram_timings(struct sdram_timing *val); 90 91 /** 92 * Configure DDR PHY 93 */ 94 int config_ddr_phy(struct ddr_phy_control *cfg); 95 96 /** 97 * This structure represents the DDR registers on AM33XX devices. 98 */ 99 struct ddr_regs { 100 unsigned int resv0[7]; 101 unsigned int cm0csratio; /* offset 0x01C */ 102 unsigned int cm0csforce; /* offset 0x020 */ 103 unsigned int cm0csdelay; /* offset 0x024 */ 104 unsigned int cm0dldiff; /* offset 0x028 */ 105 unsigned int cm0iclkout; /* offset 0x02C */ 106 unsigned int resv1[8]; 107 unsigned int cm1csratio; /* offset 0x050 */ 108 unsigned int cm1csforce; /* offset 0x054 */ 109 unsigned int cm1csdelay; /* offset 0x058 */ 110 unsigned int cm1dldiff; /* offset 0x05C */ 111 unsigned int cm1iclkout; /* offset 0x060 */ 112 unsigned int resv2[8]; 113 unsigned int cm2csratio; /* offset 0x084 */ 114 unsigned int cm2csforce; /* offset 0x088 */ 115 unsigned int cm2csdelay; /* offset 0x08C */ 116 unsigned int cm2dldiff; /* offset 0x090 */ 117 unsigned int cm2iclkout; /* offset 0x094 */ 118 unsigned int resv3[12]; 119 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 120 unsigned int dt0rdsratio1; /* offset 0x0CC */ 121 unsigned int resv4[3]; 122 unsigned int dt0wdsratio0; /* offset 0x0DC */ 123 unsigned int dt0wdsratio1; /* offset 0x0E0 */ 124 unsigned int resv5[3]; 125 unsigned int dt0wiratio0; /* offset 0x0F0 */ 126 unsigned int dt0wiratio1; /* offset 0x0F4 */ 127 unsigned int dt0giratio0; /* offset 0x0FC */ 128 unsigned int dt0giratio1; /* offset 0x100 */ 129 unsigned int resv6[1]; 130 unsigned int dt0fwsratio0; /* offset 0x108 */ 131 unsigned int dt0fwsratio1; /* offset 0x10C */ 132 unsigned int resv7[4]; 133 unsigned int dt0wrsratio0; /* offset 0x120 */ 134 unsigned int dt0wrsratio1; /* offset 0x124 */ 135 unsigned int resv8[3]; 136 unsigned int dt0rdelays0; /* offset 0x134 */ 137 unsigned int dt0dldiff0; /* offset 0x138 */ 138 unsigned int resv9[39]; 139 unsigned int dt1rdelays0; /* offset 0x1D8 */ 140 }; 141 142 /** 143 * Encapsulates DDR CMD control registers. 144 */ 145 struct cmd_control { 146 unsigned long cmd0csratio; 147 unsigned long cmd0csforce; 148 unsigned long cmd0csdelay; 149 unsigned long cmd0dldiff; 150 unsigned long cmd0iclkout; 151 unsigned long cmd1csratio; 152 unsigned long cmd1csforce; 153 unsigned long cmd1csdelay; 154 unsigned long cmd1dldiff; 155 unsigned long cmd1iclkout; 156 unsigned long cmd2csratio; 157 unsigned long cmd2csforce; 158 unsigned long cmd2csdelay; 159 unsigned long cmd2dldiff; 160 unsigned long cmd2iclkout; 161 }; 162 163 /** 164 * Encapsulates DDR DATA registers. 165 */ 166 struct ddr_data { 167 unsigned long datardsratio0; 168 unsigned long datardsratio1; 169 unsigned long datawdsratio0; 170 unsigned long datawdsratio1; 171 unsigned long datawiratio0; 172 unsigned long datawiratio1; 173 unsigned long datagiratio0; 174 unsigned long datagiratio1; 175 unsigned long datafwsratio0; 176 unsigned long datafwsratio1; 177 unsigned long datawrsratio0; 178 unsigned long datawrsratio1; 179 unsigned long datadldiff0; 180 }; 181 182 /** 183 * Configure DDR CMD control registers 184 */ 185 int config_cmd_ctrl(const struct cmd_control *cmd); 186 187 /** 188 * Configure DDR DATA registers 189 */ 190 int config_ddr_data(int data_macrono, const struct ddr_data *data); 191 192 /** 193 * This structure represents the DDR io control on AM33XX devices. 194 */ 195 struct ddr_cmdtctrl { 196 unsigned int resv1[1]; 197 unsigned int cm0ioctl; 198 unsigned int cm1ioctl; 199 unsigned int cm2ioctl; 200 unsigned int resv2[12]; 201 unsigned int dt0ioctl; 202 unsigned int dt1ioctl; 203 }; 204 205 /** 206 * Encapsulates DDR CMD & DATA io control registers. 207 */ 208 struct ddr_ioctrl { 209 unsigned long cmd1ctl; 210 unsigned long cmd2ctl; 211 unsigned long cmd3ctl; 212 unsigned long data1ctl; 213 unsigned long data2ctl; 214 }; 215 216 /** 217 * Configure DDR io control registers 218 */ 219 int config_io_ctrl(struct ddr_ioctrl *ioctrl); 220 221 struct ddr_ctrl { 222 unsigned int ddrioctrl; 223 unsigned int resv1[325]; 224 unsigned int ddrckectrl; 225 }; 226 227 void config_ddr(short ddr_type); 228 229 #endif /* _DDR_DEFS_H */ 230