1f87fa62aSChandan Nath /* 2f87fa62aSChandan Nath * clock.h 3f87fa62aSChandan Nath * 4f87fa62aSChandan Nath * clock header 5f87fa62aSChandan Nath * 6b43c17cbSMatt Porter * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ 7f87fa62aSChandan Nath * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9f87fa62aSChandan Nath */ 10f87fa62aSChandan Nath 11f87fa62aSChandan Nath #ifndef _CLOCKS_H_ 12f87fa62aSChandan Nath #define _CLOCKS_H_ 13f87fa62aSChandan Nath 14f87fa62aSChandan Nath #include <asm/arch/clocks_am33xx.h> 15f87fa62aSChandan Nath 16*94d77fb6SLokesh Vutla #define LDELAY 1000000 17*94d77fb6SLokesh Vutla 18*94d77fb6SLokesh Vutla /* CM_CLKMODE_DPLL */ 19*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 20*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 21*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 22*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 23*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 24*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 25*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 26*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 27*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 28*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 29*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_EN_SHIFT 0 30*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 31*94d77fb6SLokesh Vutla 32*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 33*94d77fb6SLokesh Vutla #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 34*94d77fb6SLokesh Vutla 35*94d77fb6SLokesh Vutla #define DPLL_EN_STOP 1 36*94d77fb6SLokesh Vutla #define DPLL_EN_MN_BYPASS 4 37*94d77fb6SLokesh Vutla #define DPLL_EN_LOW_POWER_BYPASS 5 38*94d77fb6SLokesh Vutla #define DPLL_EN_LOCK 7 39*94d77fb6SLokesh Vutla 40*94d77fb6SLokesh Vutla /* CM_IDLEST_DPLL fields */ 41*94d77fb6SLokesh Vutla #define ST_DPLL_CLK_MASK 1 42*94d77fb6SLokesh Vutla 43*94d77fb6SLokesh Vutla /* CM_CLKSEL_DPLL */ 44*94d77fb6SLokesh Vutla #define CM_CLKSEL_DPLL_M_SHIFT 8 45*94d77fb6SLokesh Vutla #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 46*94d77fb6SLokesh Vutla #define CM_CLKSEL_DPLL_N_SHIFT 0 47*94d77fb6SLokesh Vutla #define CM_CLKSEL_DPLL_N_MASK 0x7F 48*94d77fb6SLokesh Vutla 49*94d77fb6SLokesh Vutla struct dpll_params { 50*94d77fb6SLokesh Vutla u32 m; 51*94d77fb6SLokesh Vutla u32 n; 52*94d77fb6SLokesh Vutla s8 m2; 53*94d77fb6SLokesh Vutla s8 m3; 54*94d77fb6SLokesh Vutla s8 m4; 55*94d77fb6SLokesh Vutla s8 m5; 56*94d77fb6SLokesh Vutla s8 m6; 57*94d77fb6SLokesh Vutla }; 58*94d77fb6SLokesh Vutla 59*94d77fb6SLokesh Vutla struct dpll_regs { 60*94d77fb6SLokesh Vutla u32 cm_clkmode_dpll; 61*94d77fb6SLokesh Vutla u32 cm_idlest_dpll; 62*94d77fb6SLokesh Vutla u32 cm_autoidle_dpll; 63*94d77fb6SLokesh Vutla u32 cm_clksel_dpll; 64*94d77fb6SLokesh Vutla u32 cm_div_m2_dpll; 65*94d77fb6SLokesh Vutla u32 cm_div_m3_dpll; 66*94d77fb6SLokesh Vutla u32 cm_div_m4_dpll; 67*94d77fb6SLokesh Vutla u32 cm_div_m5_dpll; 68*94d77fb6SLokesh Vutla u32 cm_div_m6_dpll; 69*94d77fb6SLokesh Vutla }; 70*94d77fb6SLokesh Vutla 71*94d77fb6SLokesh Vutla extern const struct dpll_regs dpll_mpu_regs; 72*94d77fb6SLokesh Vutla extern const struct dpll_regs dpll_core_regs; 73*94d77fb6SLokesh Vutla extern const struct dpll_regs dpll_per_regs; 74*94d77fb6SLokesh Vutla extern const struct dpll_regs dpll_ddr_regs; 75*94d77fb6SLokesh Vutla extern const struct dpll_params dpll_mpu; 76*94d77fb6SLokesh Vutla extern const struct dpll_params dpll_core; 77*94d77fb6SLokesh Vutla extern const struct dpll_params dpll_per; 78*94d77fb6SLokesh Vutla extern const struct dpll_params dpll_ddr; 79*94d77fb6SLokesh Vutla 80*94d77fb6SLokesh Vutla extern const struct cm_wkuppll *cmwkup; 81*94d77fb6SLokesh Vutla 82*94d77fb6SLokesh Vutla void setup_dplls(void); 83*94d77fb6SLokesh Vutla const struct dpll_params *get_dpll_ddr_params(void); 84*94d77fb6SLokesh Vutla void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); 85*94d77fb6SLokesh Vutla 86f87fa62aSChandan Nath #endif 87