1/* 2 * dts file for Xilinx ZynqMP ep108 development board 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-ep108-clk.dtsi" 15 16/ { 17 model = "ZynqMP EP108"; 18 19 aliases { 20 mmc0 = &sdhci0; 21 mmc1 = &sdhci1; 22 serial0 = &uart0; 23 spi0 = &qspi; 24 spi1 = &spi0; 25 spi2 = &spi1; 26 usb0 = &usb0; 27 usb1 = &usb1; 28 }; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32 }; 33 34 memory { 35 device_type = "memory"; 36 reg = <0x0 0x0 0x40000000>; 37 }; 38}; 39 40&can0 { 41 status = "okay"; 42}; 43 44&gem0 { 45 status = "okay"; 46 phy-handle = <&phy0>; 47 phy-mode = "rgmii-id"; 48 phy0: phy@0 { 49 reg = <0>; 50 max-speed = <100>; 51 }; 52}; 53 54&gpio { 55 status = "okay"; 56}; 57 58&i2c0 { 59 status = "okay"; 60 clock-frequency = <400000>; 61 eeprom@54 { 62 compatible = "at,24c64"; 63 reg = <0x54>; 64 }; 65}; 66 67&i2c1 { 68 status = "okay"; 69 clock-frequency = <400000>; 70 eeprom@55 { 71 compatible = "at,24c64"; 72 reg = <0x55>; 73 }; 74}; 75 76&qspi { 77 status = "okay"; 78 flash@0 { 79 compatible = "m25p80"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 reg = <0x0>; 83 spi-tx-bus-width = <1>; 84 spi-rx-bus-width = <4>; 85 spi-max-frequency = <10000000>; 86 partition@qspi-fsbl-uboot { /* for testing purpose */ 87 label = "qspi-fsbl-uboot"; 88 reg = <0x0 0x100000>; 89 }; 90 partition@qspi-linux { /* for testing purpose */ 91 label = "qspi-linux"; 92 reg = <0x100000 0x500000>; 93 }; 94 partition@qspi-device-tree { /* for testing purpose */ 95 label = "qspi-device-tree"; 96 reg = <0x600000 0x20000>; 97 }; 98 partition@qspi-rootfs { /* for testing purpose */ 99 label = "qspi-rootfs"; 100 reg = <0x620000 0x5E0000>; 101 }; 102 }; 103}; 104 105&sata { 106 status = "okay"; 107 ceva,broken-gen2; 108}; 109 110&sdhci0 { 111 status = "okay"; 112 bus-width = <8>; 113}; 114 115&sdhci1 { 116 status = "okay"; 117}; 118 119&spi0 { 120 status = "okay"; 121 num-cs = <1>; 122 spi0_flash0: spi0_flash0@0 { 123 compatible = "m25p80"; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 spi-max-frequency = <50000000>; 127 reg = <0>; 128 129 spi0_flash0@00000000 { 130 label = "spi0_flash0"; 131 reg = <0x0 0x100000>; 132 }; 133 }; 134}; 135 136&spi1 { 137 status = "okay"; 138 num-cs = <1>; 139 spi1_flash0: spi1_flash0@0 { 140 compatible = "m25p80"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 spi-max-frequency = <50000000>; 144 reg = <0>; 145 146 spi1_flash0@00000000 { 147 label = "spi1_flash0"; 148 reg = <0x0 0x100000>; 149 }; 150 }; 151}; 152 153&uart0 { 154 status = "okay"; 155}; 156 157&usb0 { 158 status = "okay"; 159}; 160 161&dwc3_0 { 162 status = "okay"; 163 dr_mode = "peripheral"; 164 maximum-speed = "high-speed"; 165}; 166 167&usb1 { 168 status = "okay"; 169}; 170 171&dwc3_1 { 172 status = "okay"; 173 dr_mode = "host"; 174 maximum-speed = "high-speed"; 175}; 176 177&watchdog0 { 178 status = "okay"; 179}; 180 181&xlnx_dp { 182 xlnx,max-pclock-frequency = <200000>; 183}; 184 185&xlnx_dpdma { 186 xlnx,axi-clock-freq = <200000000>; 187}; 188