xref: /rk3399_rockchip-uboot/arch/arm/dts/zynqmp-ep108-clk.dtsi (revision 3ef56e61c8cbfdfdca155f5b1e2cd4d5cb5e048a) 
1/*
2 * clock specification for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11&amba {
12	misc_clk: misc_clk {
13		compatible = "fixed-clock";
14		#clock-cells = <0>;
15		clock-frequency = <25000000>;
16	};
17
18	i2c_clk: i2c_clk {
19		compatible = "fixed-clock";
20		#clock-cells = <0x0>;
21		clock-frequency = <111111111>;
22	};
23
24	sata_clk: sata_clk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <75000000>;
28	};
29
30	dp_aclk: clock0 {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <50000000>;
34		clock-accuracy = <100>;
35	};
36
37	dp_aud_clk: clock1 {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <22579200>;
41		clock-accuracy = <100>;
42	};
43};
44
45&can0 {
46	clocks = <&misc_clk &misc_clk>;
47};
48
49&gem0 {
50	clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
51};
52
53&gpio {
54	clocks = <&misc_clk>;
55};
56
57&i2c0 {
58	clocks = <&i2c_clk>;
59};
60
61&i2c1 {
62	clocks = <&i2c_clk>;
63};
64
65&qspi {
66	clocks = <&misc_clk &misc_clk>;
67};
68
69&sata {
70	clocks = <&sata_clk>;
71};
72
73&sdhci0 {
74	clocks = <&misc_clk>, <&misc_clk>;
75};
76
77&sdhci1 {
78	clocks = <&misc_clk>, <&misc_clk>;
79};
80
81&spi0 {
82	clocks = <&misc_clk &misc_clk>;
83};
84
85&spi1 {
86	clocks = <&misc_clk &misc_clk>;
87};
88
89&uart0 {
90	clocks = <&misc_clk &misc_clk>;
91};
92
93&usb0 {
94	clocks = <&misc_clk>, <&misc_clk>;
95};
96
97&usb1 {
98	clocks = <&misc_clk>, <&misc_clk>;
99};
100
101&watchdog0 {
102	clocks= <&misc_clk>;
103};
104
105&xilinx_drm {
106	clocks = <&misc_clk>;
107};
108
109&xlnx_dp {
110	clocks = <&dp_aclk>, <&dp_aud_clk>;
111};
112
113&xlnx_dp_snd_codec0 {
114	clocks = <&dp_aud_clk>;
115};
116
117&xlnx_dpdma {
118	clocks = <&misc_clk>;
119};
120