17a1aec8dSNathan Rossi/* 27a1aec8dSNathan Rossi * Avnet PicoZed board DTS 37a1aec8dSNathan Rossi * 47a1aec8dSNathan Rossi * Copyright (C) 2015 Xilinx, Inc. 57a1aec8dSNathan Rossi * 67a1aec8dSNathan Rossi * SPDX-License-Identifier: GPL-2.0+ 77a1aec8dSNathan Rossi */ 87a1aec8dSNathan Rossi/dts-v1/; 97a1aec8dSNathan Rossi#include "zynq-7000.dtsi" 107a1aec8dSNathan Rossi 117a1aec8dSNathan Rossi/ { 127a1aec8dSNathan Rossi model = "Zynq PicoZed Board"; 137a1aec8dSNathan Rossi compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000"; 147a1aec8dSNathan Rossi 157a1aec8dSNathan Rossi aliases { 167a1aec8dSNathan Rossi serial0 = &uart1; 17*20ca6790SSiva Durga Prasad Paladugu spi0 = &qspi; 18*20ca6790SSiva Durga Prasad Paladugu mmc0 = &sdhci1; 197a1aec8dSNathan Rossi }; 207a1aec8dSNathan Rossi 21cc7978beSMichal Simek memory@0 { 227a1aec8dSNathan Rossi device_type = "memory"; 237a1aec8dSNathan Rossi reg = <0 0x40000000>; 247a1aec8dSNathan Rossi }; 257a1aec8dSNathan Rossi}; 26035c6b27SSimon Glass 27035c6b27SSimon Glass&uart1 { 28035c6b27SSimon Glass u-boot,dm-pre-reloc; 29035c6b27SSimon Glass status = "okay"; 30035c6b27SSimon Glass}; 31*20ca6790SSiva Durga Prasad Paladugu 32*20ca6790SSiva Durga Prasad Paladugu&qspi { 33*20ca6790SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 34*20ca6790SSiva Durga Prasad Paladugu status = "okay"; 35*20ca6790SSiva Durga Prasad Paladugu}; 36*20ca6790SSiva Durga Prasad Paladugu 37*20ca6790SSiva Durga Prasad Paladugu&sdhci1 { 38*20ca6790SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 39*20ca6790SSiva Durga Prasad Paladugu status = "okay"; 40*20ca6790SSiva Durga Prasad Paladugu}; 41