179ce91baSTom Warren/include/ "skeleton.dtsi" 279ce91baSTom Warren 379ce91baSTom Warren/ { 479ce91baSTom Warren compatible = "nvidia,tegra30"; 5083bbbbeSTom Warren 6083bbbbeSTom Warren tegra_car: clock@60006000 { 7083bbbbeSTom Warren compatible = "nvidia,tegra30-car", "nvidia,tegra20-car"; 8083bbbbeSTom Warren reg = <0x60006000 0x1000>; 9083bbbbeSTom Warren #clock-cells = <1>; 10083bbbbeSTom Warren }; 11083bbbbeSTom Warren 12*64e6ec1dSAllen Martin apbdma: dma { 13*64e6ec1dSAllen Martin compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 14*64e6ec1dSAllen Martin reg = <0x6000a000 0x1400>; 15*64e6ec1dSAllen Martin interrupts = <0 104 0x04 16*64e6ec1dSAllen Martin 0 105 0x04 17*64e6ec1dSAllen Martin 0 106 0x04 18*64e6ec1dSAllen Martin 0 107 0x04 19*64e6ec1dSAllen Martin 0 108 0x04 20*64e6ec1dSAllen Martin 0 109 0x04 21*64e6ec1dSAllen Martin 0 110 0x04 22*64e6ec1dSAllen Martin 0 111 0x04 23*64e6ec1dSAllen Martin 0 112 0x04 24*64e6ec1dSAllen Martin 0 113 0x04 25*64e6ec1dSAllen Martin 0 114 0x04 26*64e6ec1dSAllen Martin 0 115 0x04 27*64e6ec1dSAllen Martin 0 116 0x04 28*64e6ec1dSAllen Martin 0 117 0x04 29*64e6ec1dSAllen Martin 0 118 0x04 30*64e6ec1dSAllen Martin 0 119 0x04 31*64e6ec1dSAllen Martin 0 128 0x04 32*64e6ec1dSAllen Martin 0 129 0x04 33*64e6ec1dSAllen Martin 0 130 0x04 34*64e6ec1dSAllen Martin 0 131 0x04 35*64e6ec1dSAllen Martin 0 132 0x04 36*64e6ec1dSAllen Martin 0 133 0x04 37*64e6ec1dSAllen Martin 0 134 0x04 38*64e6ec1dSAllen Martin 0 135 0x04 39*64e6ec1dSAllen Martin 0 136 0x04 40*64e6ec1dSAllen Martin 0 137 0x04 41*64e6ec1dSAllen Martin 0 138 0x04 42*64e6ec1dSAllen Martin 0 139 0x04 43*64e6ec1dSAllen Martin 0 140 0x04 44*64e6ec1dSAllen Martin 0 141 0x04 45*64e6ec1dSAllen Martin 0 142 0x04 46*64e6ec1dSAllen Martin 0 143 0x04>; 47*64e6ec1dSAllen Martin }; 48*64e6ec1dSAllen Martin 49083bbbbeSTom Warren i2c@7000c000 { 50083bbbbeSTom Warren #address-cells = <1>; 51083bbbbeSTom Warren #size-cells = <0>; 52083bbbbeSTom Warren compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 53083bbbbeSTom Warren reg = <0x7000C000 0x100>; 54083bbbbeSTom Warren /* PERIPH_ID_I2C1, CLK_M */ 55083bbbbeSTom Warren clocks = <&tegra_car 12>; 56083bbbbeSTom Warren }; 57083bbbbeSTom Warren 58083bbbbeSTom Warren i2c@7000c400 { 59083bbbbeSTom Warren #address-cells = <1>; 60083bbbbeSTom Warren #size-cells = <0>; 61083bbbbeSTom Warren compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 62083bbbbeSTom Warren reg = <0x7000C400 0x100>; 63083bbbbeSTom Warren /* PERIPH_ID_I2C2, CLK_M */ 64083bbbbeSTom Warren clocks = <&tegra_car 54>; 65083bbbbeSTom Warren }; 66083bbbbeSTom Warren 67083bbbbeSTom Warren i2c@7000c500 { 68083bbbbeSTom Warren #address-cells = <1>; 69083bbbbeSTom Warren #size-cells = <0>; 70083bbbbeSTom Warren compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 71083bbbbeSTom Warren reg = <0x7000C500 0x100>; 72083bbbbeSTom Warren /* PERIPH_ID_I2C3, CLK_M */ 73083bbbbeSTom Warren clocks = <&tegra_car 67>; 74083bbbbeSTom Warren }; 75083bbbbeSTom Warren 76083bbbbeSTom Warren i2c@7000c700 { 77083bbbbeSTom Warren #address-cells = <1>; 78083bbbbeSTom Warren #size-cells = <0>; 79083bbbbeSTom Warren compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 80083bbbbeSTom Warren reg = <0x7000C700 0x100>; 81083bbbbeSTom Warren /* PERIPH_ID_I2C4, CLK_M */ 82083bbbbeSTom Warren clocks = <&tegra_car 103>; 83083bbbbeSTom Warren }; 84083bbbbeSTom Warren 85083bbbbeSTom Warren i2c@7000d000 { 86083bbbbeSTom Warren #address-cells = <1>; 87083bbbbeSTom Warren #size-cells = <0>; 88083bbbbeSTom Warren compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 89083bbbbeSTom Warren reg = <0x7000D000 0x100>; 90083bbbbeSTom Warren /* PERIPH_ID_I2C_DVC, CLK_M */ 91083bbbbeSTom Warren clocks = <&tegra_car 47>; 92083bbbbeSTom Warren }; 9379ce91baSTom Warren}; 94