1bf78b271SMarcel Ziswiler/dts-v1/; 2bf78b271SMarcel Ziswiler 3bf78b271SMarcel Ziswiler#include "tegra30.dtsi" 4bf78b271SMarcel Ziswiler 5bf78b271SMarcel Ziswiler/ { 6bf78b271SMarcel Ziswiler model = "Toradex Apalis T30"; 7bf78b271SMarcel Ziswiler compatible = "toradex,apalis_t30", "nvidia,tegra30"; 8bf78b271SMarcel Ziswiler 99aafef4fSMarcel Ziswiler chosen { 109aafef4fSMarcel Ziswiler stdout-path = &uarta; 119aafef4fSMarcel Ziswiler }; 129aafef4fSMarcel Ziswiler 13bf78b271SMarcel Ziswiler aliases { 14bf78b271SMarcel Ziswiler i2c0 = "/i2c@7000d000"; 15bf78b271SMarcel Ziswiler i2c1 = "/i2c@7000c000"; 16bf78b271SMarcel Ziswiler i2c2 = "/i2c@7000c500"; 17bf78b271SMarcel Ziswiler i2c3 = "/i2c@7000c700"; 1867748a73SStephen Warren mmc0 = "/sdhci@78000600"; 1967748a73SStephen Warren mmc1 = "/sdhci@78000400"; 2067748a73SStephen Warren mmc2 = "/sdhci@78000000"; 21cbaeceabSMarcel Ziswiler spi0 = "/spi@7000d400"; 22cbaeceabSMarcel Ziswiler spi1 = "/spi@7000dc00"; 23cbaeceabSMarcel Ziswiler spi2 = "/spi@7000de00"; 24cbaeceabSMarcel Ziswiler spi3 = "/spi@7000da00"; 25bf78b271SMarcel Ziswiler usb0 = "/usb@7d000000"; 26bf78b271SMarcel Ziswiler usb1 = "/usb@7d004000"; 27bf78b271SMarcel Ziswiler usb2 = "/usb@7d008000"; 28bf78b271SMarcel Ziswiler }; 29bf78b271SMarcel Ziswiler 30bf78b271SMarcel Ziswiler memory { 31bf78b271SMarcel Ziswiler device_type = "memory"; 32bf78b271SMarcel Ziswiler reg = <0x80000000 0x40000000>; 33bf78b271SMarcel Ziswiler }; 34bf78b271SMarcel Ziswiler 35bf78b271SMarcel Ziswiler pcie-controller@00003000 { 36bf78b271SMarcel Ziswiler status = "okay"; 37bf78b271SMarcel Ziswiler avdd-pexa-supply = <&vdd2_reg>; 38bf78b271SMarcel Ziswiler vdd-pexa-supply = <&vdd2_reg>; 39bf78b271SMarcel Ziswiler avdd-pexb-supply = <&vdd2_reg>; 40bf78b271SMarcel Ziswiler vdd-pexb-supply = <&vdd2_reg>; 41bf78b271SMarcel Ziswiler avdd-pex-pll-supply = <&vdd2_reg>; 42bf78b271SMarcel Ziswiler avdd-plle-supply = <&ldo6_reg>; 43bf78b271SMarcel Ziswiler vddio-pex-ctl-supply = <&sys_3v3_reg>; 44bf78b271SMarcel Ziswiler hvdd-pex-supply = <&sys_3v3_reg>; 45bf78b271SMarcel Ziswiler 46bf78b271SMarcel Ziswiler pci@1,0 { 47bf78b271SMarcel Ziswiler nvidia,num-lanes = <4>; 48bf78b271SMarcel Ziswiler }; 49bf78b271SMarcel Ziswiler 50bf78b271SMarcel Ziswiler pci@2,0 { 51bf78b271SMarcel Ziswiler nvidia,num-lanes = <1>; 52bf78b271SMarcel Ziswiler }; 53bf78b271SMarcel Ziswiler 54bf78b271SMarcel Ziswiler pci@3,0 { 55bf78b271SMarcel Ziswiler status = "okay"; 56bf78b271SMarcel Ziswiler nvidia,num-lanes = <1>; 57bf78b271SMarcel Ziswiler }; 58bf78b271SMarcel Ziswiler }; 59bf78b271SMarcel Ziswiler 60bf78b271SMarcel Ziswiler /* 61bf78b271SMarcel Ziswiler * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier 62bf78b271SMarcel Ziswiler * board) 63bf78b271SMarcel Ziswiler */ 64bf78b271SMarcel Ziswiler i2c@7000c000 { 65bf78b271SMarcel Ziswiler status = "okay"; 66bf78b271SMarcel Ziswiler clock-frequency = <100000>; 67bf78b271SMarcel Ziswiler }; 68bf78b271SMarcel Ziswiler 69bf78b271SMarcel Ziswiler /* GEN2_I2C: unused */ 70bf78b271SMarcel Ziswiler 71bf78b271SMarcel Ziswiler /* 72bf78b271SMarcel Ziswiler * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on 73bf78b271SMarcel Ziswiler * carrier board) 74bf78b271SMarcel Ziswiler */ 75bf78b271SMarcel Ziswiler i2c@7000c500 { 76bf78b271SMarcel Ziswiler status = "okay"; 77bf78b271SMarcel Ziswiler clock-frequency = <100000>; 78bf78b271SMarcel Ziswiler }; 79bf78b271SMarcel Ziswiler 80bf78b271SMarcel Ziswiler /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ 81bf78b271SMarcel Ziswiler i2c@7000c700 { 82bf78b271SMarcel Ziswiler status = "okay"; 83bf78b271SMarcel Ziswiler clock-frequency = <100000>; 84bf78b271SMarcel Ziswiler }; 85bf78b271SMarcel Ziswiler 86bf78b271SMarcel Ziswiler /* 87bf78b271SMarcel Ziswiler * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 88bf78b271SMarcel Ziswiler * touch screen controller 89bf78b271SMarcel Ziswiler */ 90bf78b271SMarcel Ziswiler i2c@7000d000 { 91bf78b271SMarcel Ziswiler status = "okay"; 92bf78b271SMarcel Ziswiler clock-frequency = <100000>; 93bf78b271SMarcel Ziswiler 94bf78b271SMarcel Ziswiler pmic: tps65911@2d { 95bf78b271SMarcel Ziswiler compatible = "ti,tps65911"; 96bf78b271SMarcel Ziswiler reg = <0x2d>; 97bf78b271SMarcel Ziswiler 98bf78b271SMarcel Ziswiler interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 99bf78b271SMarcel Ziswiler #interrupt-cells = <2>; 100bf78b271SMarcel Ziswiler interrupt-controller; 101bf78b271SMarcel Ziswiler 102bf78b271SMarcel Ziswiler ti,system-power-controller; 103bf78b271SMarcel Ziswiler 104bf78b271SMarcel Ziswiler #gpio-cells = <2>; 105bf78b271SMarcel Ziswiler gpio-controller; 106bf78b271SMarcel Ziswiler 107bf78b271SMarcel Ziswiler vcc1-supply = <&sys_3v3_reg>; 108bf78b271SMarcel Ziswiler vcc2-supply = <&sys_3v3_reg>; 109bf78b271SMarcel Ziswiler vcc3-supply = <&vio_reg>; 110bf78b271SMarcel Ziswiler vcc4-supply = <&sys_3v3_reg>; 111bf78b271SMarcel Ziswiler vcc5-supply = <&sys_3v3_reg>; 112bf78b271SMarcel Ziswiler vcc6-supply = <&vio_reg>; 113bf78b271SMarcel Ziswiler vcc7-supply = <&charge_pump_5v0_reg>; 114bf78b271SMarcel Ziswiler vccio-supply = <&sys_3v3_reg>; 115bf78b271SMarcel Ziswiler 116bf78b271SMarcel Ziswiler regulators { 117bf78b271SMarcel Ziswiler #address-cells = <1>; 118bf78b271SMarcel Ziswiler #size-cells = <0>; 119bf78b271SMarcel Ziswiler 120bf78b271SMarcel Ziswiler /* SW1: +V1.35_VDDIO_DDR */ 121bf78b271SMarcel Ziswiler vdd1_reg: vdd1 { 122bf78b271SMarcel Ziswiler regulator-name = "vddio_ddr_1v35"; 123bf78b271SMarcel Ziswiler regulator-min-microvolt = <1350000>; 124bf78b271SMarcel Ziswiler regulator-max-microvolt = <1350000>; 125bf78b271SMarcel Ziswiler regulator-always-on; 126bf78b271SMarcel Ziswiler }; 127bf78b271SMarcel Ziswiler 128bf78b271SMarcel Ziswiler /* SW2: +V1.05 */ 129bf78b271SMarcel Ziswiler vdd2_reg: vdd2 { 130bf78b271SMarcel Ziswiler regulator-name = 131bf78b271SMarcel Ziswiler "vdd_pexa,vdd_pexb,vdd_sata"; 132bf78b271SMarcel Ziswiler regulator-min-microvolt = <1050000>; 133bf78b271SMarcel Ziswiler regulator-max-microvolt = <1050000>; 134bf78b271SMarcel Ziswiler }; 135bf78b271SMarcel Ziswiler 136bf78b271SMarcel Ziswiler /* SW CTRL: +V1.0_VDD_CPU */ 137bf78b271SMarcel Ziswiler vddctrl_reg: vddctrl { 138bf78b271SMarcel Ziswiler regulator-name = "vdd_cpu,vdd_sys"; 139bf78b271SMarcel Ziswiler regulator-min-microvolt = <1150000>; 140bf78b271SMarcel Ziswiler regulator-max-microvolt = <1150000>; 141bf78b271SMarcel Ziswiler regulator-always-on; 142bf78b271SMarcel Ziswiler }; 143bf78b271SMarcel Ziswiler 144bf78b271SMarcel Ziswiler /* SWIO: +V1.8 */ 145bf78b271SMarcel Ziswiler vio_reg: vio { 146bf78b271SMarcel Ziswiler regulator-name = "vdd_1v8_gen"; 147bf78b271SMarcel Ziswiler regulator-min-microvolt = <1800000>; 148bf78b271SMarcel Ziswiler regulator-max-microvolt = <1800000>; 149bf78b271SMarcel Ziswiler regulator-always-on; 150bf78b271SMarcel Ziswiler }; 151bf78b271SMarcel Ziswiler 152bf78b271SMarcel Ziswiler /* LDO1: unused */ 153bf78b271SMarcel Ziswiler 154bf78b271SMarcel Ziswiler /* 155bf78b271SMarcel Ziswiler * EN_+V3.3 switching via FET: 156bf78b271SMarcel Ziswiler * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 157bf78b271SMarcel Ziswiler * see also v3_3 fixed supply 158bf78b271SMarcel Ziswiler */ 159bf78b271SMarcel Ziswiler ldo2_reg: ldo2 { 160bf78b271SMarcel Ziswiler regulator-name = "en_3v3"; 161bf78b271SMarcel Ziswiler regulator-min-microvolt = <3300000>; 162bf78b271SMarcel Ziswiler regulator-max-microvolt = <3300000>; 163bf78b271SMarcel Ziswiler regulator-always-on; 164bf78b271SMarcel Ziswiler }; 165bf78b271SMarcel Ziswiler 166bf78b271SMarcel Ziswiler /* +V1.2_CSI */ 167bf78b271SMarcel Ziswiler ldo3_reg: ldo3 { 168bf78b271SMarcel Ziswiler regulator-name = 169bf78b271SMarcel Ziswiler "avdd_dsi_csi,pwrdet_mipi"; 170bf78b271SMarcel Ziswiler regulator-min-microvolt = <1200000>; 171bf78b271SMarcel Ziswiler regulator-max-microvolt = <1200000>; 172bf78b271SMarcel Ziswiler }; 173bf78b271SMarcel Ziswiler 174bf78b271SMarcel Ziswiler /* +V1.2_VDD_RTC */ 175bf78b271SMarcel Ziswiler ldo4_reg: ldo4 { 176bf78b271SMarcel Ziswiler regulator-name = "vdd_rtc"; 177bf78b271SMarcel Ziswiler regulator-min-microvolt = <1200000>; 178bf78b271SMarcel Ziswiler regulator-max-microvolt = <1200000>; 179bf78b271SMarcel Ziswiler regulator-always-on; 180bf78b271SMarcel Ziswiler }; 181bf78b271SMarcel Ziswiler 182bf78b271SMarcel Ziswiler /* 183bf78b271SMarcel Ziswiler * +V2.8_AVDD_VDAC: 184bf78b271SMarcel Ziswiler * only required for analog RGB 185bf78b271SMarcel Ziswiler */ 186bf78b271SMarcel Ziswiler ldo5_reg: ldo5 { 187bf78b271SMarcel Ziswiler regulator-name = "avdd_vdac"; 188bf78b271SMarcel Ziswiler regulator-min-microvolt = <2800000>; 189bf78b271SMarcel Ziswiler regulator-max-microvolt = <2800000>; 190bf78b271SMarcel Ziswiler regulator-always-on; 191bf78b271SMarcel Ziswiler }; 192bf78b271SMarcel Ziswiler 193bf78b271SMarcel Ziswiler /* 194bf78b271SMarcel Ziswiler * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 195bf78b271SMarcel Ziswiler * but LDO6 can't set voltage in 50mV 196bf78b271SMarcel Ziswiler * granularity 197bf78b271SMarcel Ziswiler */ 198bf78b271SMarcel Ziswiler ldo6_reg: ldo6 { 199bf78b271SMarcel Ziswiler regulator-name = "avdd_plle"; 200bf78b271SMarcel Ziswiler regulator-min-microvolt = <1100000>; 201bf78b271SMarcel Ziswiler regulator-max-microvolt = <1100000>; 202bf78b271SMarcel Ziswiler }; 203bf78b271SMarcel Ziswiler 204bf78b271SMarcel Ziswiler /* +V1.2_AVDD_PLL */ 205bf78b271SMarcel Ziswiler ldo7_reg: ldo7 { 206bf78b271SMarcel Ziswiler regulator-name = "avdd_pll"; 207bf78b271SMarcel Ziswiler regulator-min-microvolt = <1200000>; 208bf78b271SMarcel Ziswiler regulator-max-microvolt = <1200000>; 209bf78b271SMarcel Ziswiler regulator-always-on; 210bf78b271SMarcel Ziswiler }; 211bf78b271SMarcel Ziswiler 212bf78b271SMarcel Ziswiler /* +V1.0_VDD_DDR_HS */ 213bf78b271SMarcel Ziswiler ldo8_reg: ldo8 { 214bf78b271SMarcel Ziswiler regulator-name = "vdd_ddr_hs"; 215bf78b271SMarcel Ziswiler regulator-min-microvolt = <1000000>; 216bf78b271SMarcel Ziswiler regulator-max-microvolt = <1000000>; 217bf78b271SMarcel Ziswiler regulator-always-on; 218bf78b271SMarcel Ziswiler }; 219bf78b271SMarcel Ziswiler }; 220bf78b271SMarcel Ziswiler }; 221bf78b271SMarcel Ziswiler }; 222bf78b271SMarcel Ziswiler 223bf78b271SMarcel Ziswiler /* SPI1: Apalis SPI1 */ 224bf78b271SMarcel Ziswiler spi@7000d400 { 225bf78b271SMarcel Ziswiler status = "okay"; 226bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 227bf78b271SMarcel Ziswiler }; 228bf78b271SMarcel Ziswiler 229bf78b271SMarcel Ziswiler /* SPI4: CAN2 */ 230bf78b271SMarcel Ziswiler spi@7000da00 { 231bf78b271SMarcel Ziswiler status = "okay"; 232bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 233bf78b271SMarcel Ziswiler }; 234bf78b271SMarcel Ziswiler 235bf78b271SMarcel Ziswiler /* SPI5: Apalis SPI2 */ 236bf78b271SMarcel Ziswiler spi@7000dc00 { 237bf78b271SMarcel Ziswiler status = "okay"; 238bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 239bf78b271SMarcel Ziswiler }; 240bf78b271SMarcel Ziswiler 241bf78b271SMarcel Ziswiler /* SPI6: CAN1 */ 242bf78b271SMarcel Ziswiler spi@7000de00 { 243bf78b271SMarcel Ziswiler status = "okay"; 244bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 245bf78b271SMarcel Ziswiler }; 246bf78b271SMarcel Ziswiler 247bf78b271SMarcel Ziswiler sdhci@78000000 { 248bf78b271SMarcel Ziswiler status = "okay"; 249bf78b271SMarcel Ziswiler bus-width = <4>; 25072731118SMarcel Ziswiler /* SD1_CD# */ 25172731118SMarcel Ziswiler cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; 252bf78b271SMarcel Ziswiler }; 253bf78b271SMarcel Ziswiler 254bf78b271SMarcel Ziswiler sdhci@78000400 { 255bf78b271SMarcel Ziswiler status = "okay"; 256bf78b271SMarcel Ziswiler bus-width = <8>; 25772731118SMarcel Ziswiler /* MMC1_CD# */ 25872731118SMarcel Ziswiler cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 259bf78b271SMarcel Ziswiler }; 260bf78b271SMarcel Ziswiler 261bf78b271SMarcel Ziswiler sdhci@78000600 { 262bf78b271SMarcel Ziswiler status = "okay"; 263bf78b271SMarcel Ziswiler bus-width = <8>; 264bf78b271SMarcel Ziswiler non-removable; 265bf78b271SMarcel Ziswiler }; 266bf78b271SMarcel Ziswiler 267bf78b271SMarcel Ziswiler /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ 268bf78b271SMarcel Ziswiler usb@7d000000 { 269bf78b271SMarcel Ziswiler status = "okay"; 27029ce9995SMarcel Ziswiler dr_mode = "otg"; 27172731118SMarcel Ziswiler /* USBO1_EN */ 2722b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 273bf78b271SMarcel Ziswiler }; 274bf78b271SMarcel Ziswiler 275bf78b271SMarcel Ziswiler /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ 276bf78b271SMarcel Ziswiler usb@7d004000 { 277bf78b271SMarcel Ziswiler status = "okay"; 27872731118SMarcel Ziswiler /* USBH_EN */ 2792b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 280bf78b271SMarcel Ziswiler }; 281bf78b271SMarcel Ziswiler 282bf78b271SMarcel Ziswiler /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ 283bf78b271SMarcel Ziswiler usb@7d008000 { 284bf78b271SMarcel Ziswiler status = "okay"; 28572731118SMarcel Ziswiler /* USBH_EN */ 2862b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 287bf78b271SMarcel Ziswiler }; 288bf78b271SMarcel Ziswiler 289*ce2f2d2aSStephen Warren clocks { 290*ce2f2d2aSStephen Warren compatible = "simple-bus"; 291*ce2f2d2aSStephen Warren #address-cells = <1>; 292*ce2f2d2aSStephen Warren #size-cells = <0>; 293*ce2f2d2aSStephen Warren 294*ce2f2d2aSStephen Warren clk32k_in: clk@0 { 295*ce2f2d2aSStephen Warren compatible = "fixed-clock"; 296*ce2f2d2aSStephen Warren reg=<0>; 297*ce2f2d2aSStephen Warren #clock-cells = <0>; 298*ce2f2d2aSStephen Warren clock-frequency = <32768>; 299*ce2f2d2aSStephen Warren }; 300*ce2f2d2aSStephen Warren clk16m: clk@1 { 301*ce2f2d2aSStephen Warren compatible = "fixed-clock"; 302*ce2f2d2aSStephen Warren reg=<1>; 303*ce2f2d2aSStephen Warren #clock-cells = <0>; 304*ce2f2d2aSStephen Warren clock-frequency = <16000000>; 305*ce2f2d2aSStephen Warren clock-output-names = "clk16m"; 306*ce2f2d2aSStephen Warren }; 307*ce2f2d2aSStephen Warren }; 308*ce2f2d2aSStephen Warren 309bf78b271SMarcel Ziswiler regulators { 310bf78b271SMarcel Ziswiler compatible = "simple-bus"; 311bf78b271SMarcel Ziswiler #address-cells = <1>; 312bf78b271SMarcel Ziswiler #size-cells = <0>; 313bf78b271SMarcel Ziswiler 314bf78b271SMarcel Ziswiler sys_3v3_reg: regulator@100 { 315bf78b271SMarcel Ziswiler compatible = "regulator-fixed"; 316bf78b271SMarcel Ziswiler reg = <100>; 317bf78b271SMarcel Ziswiler regulator-name = "3v3"; 318bf78b271SMarcel Ziswiler regulator-min-microvolt = <3300000>; 319bf78b271SMarcel Ziswiler regulator-max-microvolt = <3300000>; 320bf78b271SMarcel Ziswiler regulator-always-on; 321bf78b271SMarcel Ziswiler }; 322bf78b271SMarcel Ziswiler 323bf78b271SMarcel Ziswiler charge_pump_5v0_reg: regulator@101 { 324bf78b271SMarcel Ziswiler compatible = "regulator-fixed"; 325bf78b271SMarcel Ziswiler reg = <101>; 326bf78b271SMarcel Ziswiler regulator-name = "5v0"; 327bf78b271SMarcel Ziswiler regulator-min-microvolt = <5000000>; 328bf78b271SMarcel Ziswiler regulator-max-microvolt = <5000000>; 329bf78b271SMarcel Ziswiler regulator-always-on; 330bf78b271SMarcel Ziswiler }; 331bf78b271SMarcel Ziswiler }; 332bf78b271SMarcel Ziswiler}; 333