1bf78b271SMarcel Ziswiler/dts-v1/; 2bf78b271SMarcel Ziswiler 3bf78b271SMarcel Ziswiler#include "tegra30.dtsi" 4bf78b271SMarcel Ziswiler 5bf78b271SMarcel Ziswiler/ { 6bf78b271SMarcel Ziswiler model = "Toradex Apalis T30"; 7bf78b271SMarcel Ziswiler compatible = "toradex,apalis_t30", "nvidia,tegra30"; 8bf78b271SMarcel Ziswiler 99aafef4fSMarcel Ziswiler chosen { 109aafef4fSMarcel Ziswiler stdout-path = &uarta; 119aafef4fSMarcel Ziswiler }; 129aafef4fSMarcel Ziswiler 13bf78b271SMarcel Ziswiler aliases { 14bf78b271SMarcel Ziswiler i2c0 = "/i2c@7000d000"; 15bf78b271SMarcel Ziswiler i2c1 = "/i2c@7000c000"; 16bf78b271SMarcel Ziswiler i2c2 = "/i2c@7000c500"; 17bf78b271SMarcel Ziswiler i2c3 = "/i2c@7000c700"; 18bf78b271SMarcel Ziswiler sdhci0 = "/sdhci@78000600"; 19bf78b271SMarcel Ziswiler sdhci1 = "/sdhci@78000400"; 20bf78b271SMarcel Ziswiler sdhci2 = "/sdhci@78000000"; 21bf78b271SMarcel Ziswiler usb0 = "/usb@7d000000"; 22bf78b271SMarcel Ziswiler usb1 = "/usb@7d004000"; 23bf78b271SMarcel Ziswiler usb2 = "/usb@7d008000"; 24bf78b271SMarcel Ziswiler }; 25bf78b271SMarcel Ziswiler 26bf78b271SMarcel Ziswiler memory { 27bf78b271SMarcel Ziswiler device_type = "memory"; 28bf78b271SMarcel Ziswiler reg = <0x80000000 0x40000000>; 29bf78b271SMarcel Ziswiler }; 30bf78b271SMarcel Ziswiler 31bf78b271SMarcel Ziswiler pcie-controller@00003000 { 32bf78b271SMarcel Ziswiler status = "okay"; 33bf78b271SMarcel Ziswiler avdd-pexa-supply = <&vdd2_reg>; 34bf78b271SMarcel Ziswiler vdd-pexa-supply = <&vdd2_reg>; 35bf78b271SMarcel Ziswiler avdd-pexb-supply = <&vdd2_reg>; 36bf78b271SMarcel Ziswiler vdd-pexb-supply = <&vdd2_reg>; 37bf78b271SMarcel Ziswiler avdd-pex-pll-supply = <&vdd2_reg>; 38bf78b271SMarcel Ziswiler avdd-plle-supply = <&ldo6_reg>; 39bf78b271SMarcel Ziswiler vddio-pex-ctl-supply = <&sys_3v3_reg>; 40bf78b271SMarcel Ziswiler hvdd-pex-supply = <&sys_3v3_reg>; 41bf78b271SMarcel Ziswiler 42bf78b271SMarcel Ziswiler pci@1,0 { 43bf78b271SMarcel Ziswiler nvidia,num-lanes = <4>; 44bf78b271SMarcel Ziswiler }; 45bf78b271SMarcel Ziswiler 46bf78b271SMarcel Ziswiler pci@2,0 { 47bf78b271SMarcel Ziswiler nvidia,num-lanes = <1>; 48bf78b271SMarcel Ziswiler }; 49bf78b271SMarcel Ziswiler 50bf78b271SMarcel Ziswiler pci@3,0 { 51bf78b271SMarcel Ziswiler status = "okay"; 52bf78b271SMarcel Ziswiler nvidia,num-lanes = <1>; 53bf78b271SMarcel Ziswiler }; 54bf78b271SMarcel Ziswiler }; 55bf78b271SMarcel Ziswiler 56bf78b271SMarcel Ziswiler /* 57bf78b271SMarcel Ziswiler * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier 58bf78b271SMarcel Ziswiler * board) 59bf78b271SMarcel Ziswiler */ 60bf78b271SMarcel Ziswiler i2c@7000c000 { 61bf78b271SMarcel Ziswiler status = "okay"; 62bf78b271SMarcel Ziswiler clock-frequency = <100000>; 63bf78b271SMarcel Ziswiler }; 64bf78b271SMarcel Ziswiler 65bf78b271SMarcel Ziswiler /* GEN2_I2C: unused */ 66bf78b271SMarcel Ziswiler 67bf78b271SMarcel Ziswiler /* 68bf78b271SMarcel Ziswiler * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on 69bf78b271SMarcel Ziswiler * carrier board) 70bf78b271SMarcel Ziswiler */ 71bf78b271SMarcel Ziswiler i2c@7000c500 { 72bf78b271SMarcel Ziswiler status = "okay"; 73bf78b271SMarcel Ziswiler clock-frequency = <100000>; 74bf78b271SMarcel Ziswiler }; 75bf78b271SMarcel Ziswiler 76bf78b271SMarcel Ziswiler /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ 77bf78b271SMarcel Ziswiler i2c@7000c700 { 78bf78b271SMarcel Ziswiler status = "okay"; 79bf78b271SMarcel Ziswiler clock-frequency = <100000>; 80bf78b271SMarcel Ziswiler }; 81bf78b271SMarcel Ziswiler 82bf78b271SMarcel Ziswiler /* 83bf78b271SMarcel Ziswiler * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 84bf78b271SMarcel Ziswiler * touch screen controller 85bf78b271SMarcel Ziswiler */ 86bf78b271SMarcel Ziswiler i2c@7000d000 { 87bf78b271SMarcel Ziswiler status = "okay"; 88bf78b271SMarcel Ziswiler clock-frequency = <100000>; 89bf78b271SMarcel Ziswiler 90bf78b271SMarcel Ziswiler pmic: tps65911@2d { 91bf78b271SMarcel Ziswiler compatible = "ti,tps65911"; 92bf78b271SMarcel Ziswiler reg = <0x2d>; 93bf78b271SMarcel Ziswiler 94bf78b271SMarcel Ziswiler interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 95bf78b271SMarcel Ziswiler #interrupt-cells = <2>; 96bf78b271SMarcel Ziswiler interrupt-controller; 97bf78b271SMarcel Ziswiler 98bf78b271SMarcel Ziswiler ti,system-power-controller; 99bf78b271SMarcel Ziswiler 100bf78b271SMarcel Ziswiler #gpio-cells = <2>; 101bf78b271SMarcel Ziswiler gpio-controller; 102bf78b271SMarcel Ziswiler 103bf78b271SMarcel Ziswiler vcc1-supply = <&sys_3v3_reg>; 104bf78b271SMarcel Ziswiler vcc2-supply = <&sys_3v3_reg>; 105bf78b271SMarcel Ziswiler vcc3-supply = <&vio_reg>; 106bf78b271SMarcel Ziswiler vcc4-supply = <&sys_3v3_reg>; 107bf78b271SMarcel Ziswiler vcc5-supply = <&sys_3v3_reg>; 108bf78b271SMarcel Ziswiler vcc6-supply = <&vio_reg>; 109bf78b271SMarcel Ziswiler vcc7-supply = <&charge_pump_5v0_reg>; 110bf78b271SMarcel Ziswiler vccio-supply = <&sys_3v3_reg>; 111bf78b271SMarcel Ziswiler 112bf78b271SMarcel Ziswiler regulators { 113bf78b271SMarcel Ziswiler #address-cells = <1>; 114bf78b271SMarcel Ziswiler #size-cells = <0>; 115bf78b271SMarcel Ziswiler 116bf78b271SMarcel Ziswiler /* SW1: +V1.35_VDDIO_DDR */ 117bf78b271SMarcel Ziswiler vdd1_reg: vdd1 { 118bf78b271SMarcel Ziswiler regulator-name = "vddio_ddr_1v35"; 119bf78b271SMarcel Ziswiler regulator-min-microvolt = <1350000>; 120bf78b271SMarcel Ziswiler regulator-max-microvolt = <1350000>; 121bf78b271SMarcel Ziswiler regulator-always-on; 122bf78b271SMarcel Ziswiler }; 123bf78b271SMarcel Ziswiler 124bf78b271SMarcel Ziswiler /* SW2: +V1.05 */ 125bf78b271SMarcel Ziswiler vdd2_reg: vdd2 { 126bf78b271SMarcel Ziswiler regulator-name = 127bf78b271SMarcel Ziswiler "vdd_pexa,vdd_pexb,vdd_sata"; 128bf78b271SMarcel Ziswiler regulator-min-microvolt = <1050000>; 129bf78b271SMarcel Ziswiler regulator-max-microvolt = <1050000>; 130bf78b271SMarcel Ziswiler }; 131bf78b271SMarcel Ziswiler 132bf78b271SMarcel Ziswiler /* SW CTRL: +V1.0_VDD_CPU */ 133bf78b271SMarcel Ziswiler vddctrl_reg: vddctrl { 134bf78b271SMarcel Ziswiler regulator-name = "vdd_cpu,vdd_sys"; 135bf78b271SMarcel Ziswiler regulator-min-microvolt = <1150000>; 136bf78b271SMarcel Ziswiler regulator-max-microvolt = <1150000>; 137bf78b271SMarcel Ziswiler regulator-always-on; 138bf78b271SMarcel Ziswiler }; 139bf78b271SMarcel Ziswiler 140bf78b271SMarcel Ziswiler /* SWIO: +V1.8 */ 141bf78b271SMarcel Ziswiler vio_reg: vio { 142bf78b271SMarcel Ziswiler regulator-name = "vdd_1v8_gen"; 143bf78b271SMarcel Ziswiler regulator-min-microvolt = <1800000>; 144bf78b271SMarcel Ziswiler regulator-max-microvolt = <1800000>; 145bf78b271SMarcel Ziswiler regulator-always-on; 146bf78b271SMarcel Ziswiler }; 147bf78b271SMarcel Ziswiler 148bf78b271SMarcel Ziswiler /* LDO1: unused */ 149bf78b271SMarcel Ziswiler 150bf78b271SMarcel Ziswiler /* 151bf78b271SMarcel Ziswiler * EN_+V3.3 switching via FET: 152bf78b271SMarcel Ziswiler * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 153bf78b271SMarcel Ziswiler * see also v3_3 fixed supply 154bf78b271SMarcel Ziswiler */ 155bf78b271SMarcel Ziswiler ldo2_reg: ldo2 { 156bf78b271SMarcel Ziswiler regulator-name = "en_3v3"; 157bf78b271SMarcel Ziswiler regulator-min-microvolt = <3300000>; 158bf78b271SMarcel Ziswiler regulator-max-microvolt = <3300000>; 159bf78b271SMarcel Ziswiler regulator-always-on; 160bf78b271SMarcel Ziswiler }; 161bf78b271SMarcel Ziswiler 162bf78b271SMarcel Ziswiler /* +V1.2_CSI */ 163bf78b271SMarcel Ziswiler ldo3_reg: ldo3 { 164bf78b271SMarcel Ziswiler regulator-name = 165bf78b271SMarcel Ziswiler "avdd_dsi_csi,pwrdet_mipi"; 166bf78b271SMarcel Ziswiler regulator-min-microvolt = <1200000>; 167bf78b271SMarcel Ziswiler regulator-max-microvolt = <1200000>; 168bf78b271SMarcel Ziswiler }; 169bf78b271SMarcel Ziswiler 170bf78b271SMarcel Ziswiler /* +V1.2_VDD_RTC */ 171bf78b271SMarcel Ziswiler ldo4_reg: ldo4 { 172bf78b271SMarcel Ziswiler regulator-name = "vdd_rtc"; 173bf78b271SMarcel Ziswiler regulator-min-microvolt = <1200000>; 174bf78b271SMarcel Ziswiler regulator-max-microvolt = <1200000>; 175bf78b271SMarcel Ziswiler regulator-always-on; 176bf78b271SMarcel Ziswiler }; 177bf78b271SMarcel Ziswiler 178bf78b271SMarcel Ziswiler /* 179bf78b271SMarcel Ziswiler * +V2.8_AVDD_VDAC: 180bf78b271SMarcel Ziswiler * only required for analog RGB 181bf78b271SMarcel Ziswiler */ 182bf78b271SMarcel Ziswiler ldo5_reg: ldo5 { 183bf78b271SMarcel Ziswiler regulator-name = "avdd_vdac"; 184bf78b271SMarcel Ziswiler regulator-min-microvolt = <2800000>; 185bf78b271SMarcel Ziswiler regulator-max-microvolt = <2800000>; 186bf78b271SMarcel Ziswiler regulator-always-on; 187bf78b271SMarcel Ziswiler }; 188bf78b271SMarcel Ziswiler 189bf78b271SMarcel Ziswiler /* 190bf78b271SMarcel Ziswiler * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 191bf78b271SMarcel Ziswiler * but LDO6 can't set voltage in 50mV 192bf78b271SMarcel Ziswiler * granularity 193bf78b271SMarcel Ziswiler */ 194bf78b271SMarcel Ziswiler ldo6_reg: ldo6 { 195bf78b271SMarcel Ziswiler regulator-name = "avdd_plle"; 196bf78b271SMarcel Ziswiler regulator-min-microvolt = <1100000>; 197bf78b271SMarcel Ziswiler regulator-max-microvolt = <1100000>; 198bf78b271SMarcel Ziswiler }; 199bf78b271SMarcel Ziswiler 200bf78b271SMarcel Ziswiler /* +V1.2_AVDD_PLL */ 201bf78b271SMarcel Ziswiler ldo7_reg: ldo7 { 202bf78b271SMarcel Ziswiler regulator-name = "avdd_pll"; 203bf78b271SMarcel Ziswiler regulator-min-microvolt = <1200000>; 204bf78b271SMarcel Ziswiler regulator-max-microvolt = <1200000>; 205bf78b271SMarcel Ziswiler regulator-always-on; 206bf78b271SMarcel Ziswiler }; 207bf78b271SMarcel Ziswiler 208bf78b271SMarcel Ziswiler /* +V1.0_VDD_DDR_HS */ 209bf78b271SMarcel Ziswiler ldo8_reg: ldo8 { 210bf78b271SMarcel Ziswiler regulator-name = "vdd_ddr_hs"; 211bf78b271SMarcel Ziswiler regulator-min-microvolt = <1000000>; 212bf78b271SMarcel Ziswiler regulator-max-microvolt = <1000000>; 213bf78b271SMarcel Ziswiler regulator-always-on; 214bf78b271SMarcel Ziswiler }; 215bf78b271SMarcel Ziswiler }; 216bf78b271SMarcel Ziswiler }; 217bf78b271SMarcel Ziswiler }; 218bf78b271SMarcel Ziswiler 219bf78b271SMarcel Ziswiler /* SPI1: Apalis SPI1 */ 220bf78b271SMarcel Ziswiler spi@7000d400 { 221bf78b271SMarcel Ziswiler status = "okay"; 222bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 223bf78b271SMarcel Ziswiler }; 224bf78b271SMarcel Ziswiler 225bf78b271SMarcel Ziswiler /* SPI4: CAN2 */ 226bf78b271SMarcel Ziswiler spi@7000da00 { 227bf78b271SMarcel Ziswiler status = "okay"; 228bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 229bf78b271SMarcel Ziswiler }; 230bf78b271SMarcel Ziswiler 231bf78b271SMarcel Ziswiler /* SPI5: Apalis SPI2 */ 232bf78b271SMarcel Ziswiler spi@7000dc00 { 233bf78b271SMarcel Ziswiler status = "okay"; 234bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 235bf78b271SMarcel Ziswiler }; 236bf78b271SMarcel Ziswiler 237bf78b271SMarcel Ziswiler /* SPI6: CAN1 */ 238bf78b271SMarcel Ziswiler spi@7000de00 { 239bf78b271SMarcel Ziswiler status = "okay"; 240bf78b271SMarcel Ziswiler spi-max-frequency = <25000000>; 241bf78b271SMarcel Ziswiler }; 242bf78b271SMarcel Ziswiler 243bf78b271SMarcel Ziswiler sdhci@78000000 { 244bf78b271SMarcel Ziswiler status = "okay"; 245bf78b271SMarcel Ziswiler bus-width = <4>; 246*2b2b50bcSSimon Glass cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; 247bf78b271SMarcel Ziswiler }; 248bf78b271SMarcel Ziswiler 249bf78b271SMarcel Ziswiler sdhci@78000400 { 250bf78b271SMarcel Ziswiler status = "okay"; 251bf78b271SMarcel Ziswiler bus-width = <8>; 252*2b2b50bcSSimon Glass cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 253bf78b271SMarcel Ziswiler }; 254bf78b271SMarcel Ziswiler 255bf78b271SMarcel Ziswiler sdhci@78000600 { 256bf78b271SMarcel Ziswiler status = "okay"; 257bf78b271SMarcel Ziswiler bus-width = <8>; 258bf78b271SMarcel Ziswiler non-removable; 259bf78b271SMarcel Ziswiler }; 260bf78b271SMarcel Ziswiler 261bf78b271SMarcel Ziswiler /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ 262bf78b271SMarcel Ziswiler usb@7d000000 { 263bf78b271SMarcel Ziswiler status = "okay"; 264bf78b271SMarcel Ziswiler dr_mode = "peripheral"; 265*2b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 266bf78b271SMarcel Ziswiler }; 267bf78b271SMarcel Ziswiler 268bf78b271SMarcel Ziswiler /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ 269bf78b271SMarcel Ziswiler usb@7d004000 { 270bf78b271SMarcel Ziswiler status = "okay"; 271*2b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 272bf78b271SMarcel Ziswiler phy_type = "utmi"; 273bf78b271SMarcel Ziswiler }; 274bf78b271SMarcel Ziswiler 275bf78b271SMarcel Ziswiler /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ 276bf78b271SMarcel Ziswiler usb@7d008000 { 277bf78b271SMarcel Ziswiler status = "okay"; 278*2b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 279bf78b271SMarcel Ziswiler }; 280bf78b271SMarcel Ziswiler 281bf78b271SMarcel Ziswiler regulators { 282bf78b271SMarcel Ziswiler compatible = "simple-bus"; 283bf78b271SMarcel Ziswiler #address-cells = <1>; 284bf78b271SMarcel Ziswiler #size-cells = <0>; 285bf78b271SMarcel Ziswiler 286bf78b271SMarcel Ziswiler sys_3v3_reg: regulator@100 { 287bf78b271SMarcel Ziswiler compatible = "regulator-fixed"; 288bf78b271SMarcel Ziswiler reg = <100>; 289bf78b271SMarcel Ziswiler regulator-name = "3v3"; 290bf78b271SMarcel Ziswiler regulator-min-microvolt = <3300000>; 291bf78b271SMarcel Ziswiler regulator-max-microvolt = <3300000>; 292bf78b271SMarcel Ziswiler regulator-always-on; 293bf78b271SMarcel Ziswiler }; 294bf78b271SMarcel Ziswiler 295bf78b271SMarcel Ziswiler charge_pump_5v0_reg: regulator@101 { 296bf78b271SMarcel Ziswiler compatible = "regulator-fixed"; 297bf78b271SMarcel Ziswiler reg = <101>; 298bf78b271SMarcel Ziswiler regulator-name = "5v0"; 299bf78b271SMarcel Ziswiler regulator-min-microvolt = <5000000>; 300bf78b271SMarcel Ziswiler regulator-max-microvolt = <5000000>; 301bf78b271SMarcel Ziswiler regulator-always-on; 302bf78b271SMarcel Ziswiler }; 303bf78b271SMarcel Ziswiler }; 304bf78b271SMarcel Ziswiler}; 305