xref: /rk3399_rockchip-uboot/arch/arm/dts/tegra20.dtsi (revision eefe3e598e38dc4e433d5b39c2f5528ffea461e3)
1c3474ef3SSimon Glass/include/ "skeleton.dtsi"
2c3474ef3SSimon Glass
3c3474ef3SSimon Glass/ {
4c3474ef3SSimon Glass	compatible = "nvidia,tegra20";
5c3474ef3SSimon Glass	interrupt-parent = <&intc>;
6c3474ef3SSimon Glass
71f1a0212SSimon Glass	tegra_car: clock@60006000 {
81f1a0212SSimon Glass		compatible = "nvidia,tegra20-car";
91f1a0212SSimon Glass		reg = <0x60006000 0x1000>;
101f1a0212SSimon Glass		#clock-cells = <1>;
111f1a0212SSimon Glass	};
121f1a0212SSimon Glass
131f1a0212SSimon Glass	clocks {
141f1a0212SSimon Glass		#address-cells = <1>;
151f1a0212SSimon Glass		#size-cells = <0>;
161f1a0212SSimon Glass
171f1a0212SSimon Glass		osc: clock {
181f1a0212SSimon Glass			compatible = "fixed-clock";
191f1a0212SSimon Glass			#clock-cells = <0>;
201f1a0212SSimon Glass		};
211f1a0212SSimon Glass	};
221f1a0212SSimon Glass
23c3474ef3SSimon Glass	intc: interrupt-controller@50041000 {
24c3474ef3SSimon Glass		compatible = "nvidia,tegra20-gic";
25c3474ef3SSimon Glass		interrupt-controller;
26c3474ef3SSimon Glass		#interrupt-cells = <1>;
27c3474ef3SSimon Glass		reg = < 0x50041000 0x1000 >,
28c3474ef3SSimon Glass		      < 0x50040100 0x0100 >;
29c3474ef3SSimon Glass	};
30c3474ef3SSimon Glass
31c3474ef3SSimon Glass	i2c@7000c000 {
32c3474ef3SSimon Glass		#address-cells = <1>;
33c3474ef3SSimon Glass		#size-cells = <0>;
34c3474ef3SSimon Glass		compatible = "nvidia,tegra20-i2c";
35c3474ef3SSimon Glass		reg = <0x7000C000 0x100>;
36c3474ef3SSimon Glass		interrupts = < 70 >;
3734fa833aSSimon Glass		/* PERIPH_ID_I2C1, PLL_P_OUT3 */
3834fa833aSSimon Glass		clocks = <&tegra_car 12>, <&tegra_car 124>;
39c3474ef3SSimon Glass	};
40c3474ef3SSimon Glass
41c3474ef3SSimon Glass	i2c@7000c400 {
42c3474ef3SSimon Glass		#address-cells = <1>;
43c3474ef3SSimon Glass		#size-cells = <0>;
44c3474ef3SSimon Glass		compatible = "nvidia,tegra20-i2c";
45c3474ef3SSimon Glass		reg = <0x7000C400 0x100>;
46c3474ef3SSimon Glass		interrupts = < 116 >;
4734fa833aSSimon Glass		/* PERIPH_ID_I2C2, PLL_P_OUT3 */
4834fa833aSSimon Glass		clocks = <&tegra_car 54>, <&tegra_car 124>;
49c3474ef3SSimon Glass	};
50c3474ef3SSimon Glass
51c3474ef3SSimon Glass	i2c@7000c500 {
52c3474ef3SSimon Glass		#address-cells = <1>;
53c3474ef3SSimon Glass		#size-cells = <0>;
54c3474ef3SSimon Glass		compatible = "nvidia,tegra20-i2c";
55c3474ef3SSimon Glass		reg = <0x7000C500 0x100>;
56c3474ef3SSimon Glass		interrupts = < 124 >;
5734fa833aSSimon Glass		/* PERIPH_ID_I2C3, PLL_P_OUT3 */
5834fa833aSSimon Glass		clocks = <&tegra_car 67>, <&tegra_car 124>;
59c3474ef3SSimon Glass	};
60c3474ef3SSimon Glass
61c3474ef3SSimon Glass	i2c@7000d000 {
62c3474ef3SSimon Glass		#address-cells = <1>;
63c3474ef3SSimon Glass		#size-cells = <0>;
6434fa833aSSimon Glass		compatible = "nvidia,tegra20-i2c-dvc";
65c3474ef3SSimon Glass		reg = <0x7000D000 0x200>;
66c3474ef3SSimon Glass		interrupts = < 85 >;
6734fa833aSSimon Glass		/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
6834fa833aSSimon Glass		clocks = <&tegra_car 47>, <&tegra_car 124>;
69c3474ef3SSimon Glass	};
70c3474ef3SSimon Glass
71c3474ef3SSimon Glass	i2s@70002800 {
72c3474ef3SSimon Glass		#address-cells = <1>;
73c3474ef3SSimon Glass		#size-cells = <0>;
74c3474ef3SSimon Glass		compatible = "nvidia,tegra20-i2s";
75c3474ef3SSimon Glass		reg = <0x70002800 0x200>;
76c3474ef3SSimon Glass		interrupts = < 45 >;
77c3474ef3SSimon Glass		dma-channel = < 2 >;
78c3474ef3SSimon Glass	};
79c3474ef3SSimon Glass
80c3474ef3SSimon Glass	i2s@70002a00 {
81c3474ef3SSimon Glass		#address-cells = <1>;
82c3474ef3SSimon Glass		#size-cells = <0>;
83c3474ef3SSimon Glass		compatible = "nvidia,tegra20-i2s";
84c3474ef3SSimon Glass		reg = <0x70002a00 0x200>;
85c3474ef3SSimon Glass		interrupts = < 35 >;
86c3474ef3SSimon Glass		dma-channel = < 1 >;
87c3474ef3SSimon Glass	};
88c3474ef3SSimon Glass
89c3474ef3SSimon Glass	das@70000c00 {
90c3474ef3SSimon Glass		#address-cells = <1>;
91c3474ef3SSimon Glass		#size-cells = <0>;
92c3474ef3SSimon Glass		compatible = "nvidia,tegra20-das";
93c3474ef3SSimon Glass		reg = <0x70000c00 0x80>;
94c3474ef3SSimon Glass	};
95c3474ef3SSimon Glass
96c3474ef3SSimon Glass	gpio: gpio@6000d000 {
97c3474ef3SSimon Glass		compatible = "nvidia,tegra20-gpio";
98c3474ef3SSimon Glass		reg = < 0x6000d000 0x1000 >;
99c3474ef3SSimon Glass		interrupts = < 64 65 66 67 87 119 121 >;
100c3474ef3SSimon Glass		#gpio-cells = <2>;
101c3474ef3SSimon Glass		gpio-controller;
102c3474ef3SSimon Glass	};
103c3474ef3SSimon Glass
104c3474ef3SSimon Glass	pinmux: pinmux@70000000 {
105c3474ef3SSimon Glass		compatible = "nvidia,tegra20-pinmux";
106c3474ef3SSimon Glass		reg = < 0x70000014 0x10    /* Tri-state registers */
107c3474ef3SSimon Glass			0x70000080 0x20    /* Mux registers */
108c3474ef3SSimon Glass			0x700000a0 0x14    /* Pull-up/down registers */
109c3474ef3SSimon Glass			0x70000868 0xa8 >; /* Pad control registers */
110c3474ef3SSimon Glass	};
111c3474ef3SSimon Glass
112c3474ef3SSimon Glass	serial@70006000 {
113c3474ef3SSimon Glass		compatible = "nvidia,tegra20-uart";
114c3474ef3SSimon Glass		reg = <0x70006000 0x40>;
115c3474ef3SSimon Glass		reg-shift = <2>;
116c3474ef3SSimon Glass		interrupts = < 68 >;
117c3474ef3SSimon Glass	};
118c3474ef3SSimon Glass
119c3474ef3SSimon Glass	serial@70006040 {
120c3474ef3SSimon Glass		compatible = "nvidia,tegra20-uart";
121c3474ef3SSimon Glass		reg = <0x70006040 0x40>;
122c3474ef3SSimon Glass		reg-shift = <2>;
123c3474ef3SSimon Glass		interrupts = < 69 >;
124c3474ef3SSimon Glass	};
125c3474ef3SSimon Glass
126c3474ef3SSimon Glass	serial@70006200 {
127c3474ef3SSimon Glass		compatible = "nvidia,tegra20-uart";
128c3474ef3SSimon Glass		reg = <0x70006200 0x100>;
129c3474ef3SSimon Glass		reg-shift = <2>;
130c3474ef3SSimon Glass		interrupts = < 78 >;
131c3474ef3SSimon Glass	};
132c3474ef3SSimon Glass
133c3474ef3SSimon Glass	serial@70006300 {
134c3474ef3SSimon Glass		compatible = "nvidia,tegra20-uart";
135c3474ef3SSimon Glass		reg = <0x70006300 0x100>;
136c3474ef3SSimon Glass		reg-shift = <2>;
137c3474ef3SSimon Glass		interrupts = < 122 >;
138c3474ef3SSimon Glass	};
139c3474ef3SSimon Glass
140c3474ef3SSimon Glass	serial@70006400 {
141c3474ef3SSimon Glass		compatible = "nvidia,tegra20-uart";
142c3474ef3SSimon Glass		reg = <0x70006400 0x100>;
143c3474ef3SSimon Glass		reg-shift = <2>;
144c3474ef3SSimon Glass		interrupts = < 123 >;
145c3474ef3SSimon Glass	};
146c3474ef3SSimon Glass
147c3474ef3SSimon Glass	sdhci@c8000000 {
148c3474ef3SSimon Glass		compatible = "nvidia,tegra20-sdhci";
149c3474ef3SSimon Glass		reg = <0xc8000000 0x200>;
150c3474ef3SSimon Glass		interrupts = < 46 >;
151c3474ef3SSimon Glass	};
152c3474ef3SSimon Glass
153c3474ef3SSimon Glass	sdhci@c8000200 {
154c3474ef3SSimon Glass		compatible = "nvidia,tegra20-sdhci";
155c3474ef3SSimon Glass		reg = <0xc8000200 0x200>;
156c3474ef3SSimon Glass		interrupts = < 47 >;
157c3474ef3SSimon Glass	};
158c3474ef3SSimon Glass
159c3474ef3SSimon Glass	sdhci@c8000400 {
160c3474ef3SSimon Glass		compatible = "nvidia,tegra20-sdhci";
161c3474ef3SSimon Glass		reg = <0xc8000400 0x200>;
162c3474ef3SSimon Glass		interrupts = < 51 >;
163c3474ef3SSimon Glass	};
164c3474ef3SSimon Glass
165c3474ef3SSimon Glass	sdhci@c8000600 {
166c3474ef3SSimon Glass		compatible = "nvidia,tegra20-sdhci";
167c3474ef3SSimon Glass		reg = <0xc8000600 0x200>;
168c3474ef3SSimon Glass		interrupts = < 63 >;
169c3474ef3SSimon Glass	};
170c3474ef3SSimon Glass
171c3474ef3SSimon Glass	usb@c5000000 {
172c3474ef3SSimon Glass		compatible = "nvidia,tegra20-ehci", "usb-ehci";
173c3474ef3SSimon Glass		reg = <0xc5000000 0x4000>;
174c3474ef3SSimon Glass		interrupts = < 52 >;
175c3474ef3SSimon Glass		phy_type = "utmi";
1761c1cce99SSimon Glass		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
1771c1cce99SSimon Glass		nvidia,has-legacy-mode;
178c3474ef3SSimon Glass	};
179c3474ef3SSimon Glass
180c3474ef3SSimon Glass	usb@c5004000 {
181c3474ef3SSimon Glass		compatible = "nvidia,tegra20-ehci", "usb-ehci";
182c3474ef3SSimon Glass		reg = <0xc5004000 0x4000>;
183c3474ef3SSimon Glass		interrupts = < 53 >;
184c3474ef3SSimon Glass		phy_type = "ulpi";
1851c1cce99SSimon Glass		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
186c3474ef3SSimon Glass	};
187c3474ef3SSimon Glass
188c3474ef3SSimon Glass	usb@c5008000 {
189c3474ef3SSimon Glass		compatible = "nvidia,tegra20-ehci", "usb-ehci";
190c3474ef3SSimon Glass		reg = <0xc5008000 0x4000>;
191c3474ef3SSimon Glass		interrupts = < 129 >;
192c3474ef3SSimon Glass		phy_type = "utmi";
1931c1cce99SSimon Glass		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
194c3474ef3SSimon Glass	};
195c3474ef3SSimon Glass
1961f47efa8SSimon Glass	emc@7000f400 {
1971f47efa8SSimon Glass		#address-cells = < 1 >;
1981f47efa8SSimon Glass		#size-cells = < 0 >;
1991f47efa8SSimon Glass		compatible = "nvidia,tegra20-emc";
2001f47efa8SSimon Glass		reg = <0x7000f400 0x200>;
2011f47efa8SSimon Glass	};
2021f47efa8SSimon Glass
2038436fbc3SAnton Staff	kbc@7000e200 {
2048436fbc3SAnton Staff		compatible = "nvidia,tegra20-kbc";
2058436fbc3SAnton Staff		reg = <0x7000e200 0x0078>;
2068436fbc3SAnton Staff	};
207c6af2e7dSSimon Glass
208c6af2e7dSSimon Glass	nand: nand-controller@70008000 {
209c6af2e7dSSimon Glass		#address-cells = <1>;
210c6af2e7dSSimon Glass		#size-cells = <0>;
211c6af2e7dSSimon Glass		compatible = "nvidia,tegra20-nand";
212c6af2e7dSSimon Glass		reg = <0x70008000 0x100>;
213c6af2e7dSSimon Glass	};
214beca1fdeSSimon Glass
215beca1fdeSSimon Glass	pwm: pwm@7000a000 {
216beca1fdeSSimon Glass		compatible = "nvidia,tegra20-pwm";
217beca1fdeSSimon Glass		reg = <0x7000a000 0x100>;
218beca1fdeSSimon Glass		#pwm-cells = <2>;
219beca1fdeSSimon Glass	};
220beca1fdeSSimon Glass
221*eefe3e59SSimon Glass	host1x {
222*eefe3e59SSimon Glass		compatible = "nvidia,tegra20-host1x", "simple-bus";
223*eefe3e59SSimon Glass		reg = <0x50000000 0x00024000>;
224*eefe3e59SSimon Glass		interrupts = <0 65 0x04   /* mpcore syncpt */
225*eefe3e59SSimon Glass			      0 67 0x04>; /* mpcore general */
226*eefe3e59SSimon Glass		status = "disabled";
227*eefe3e59SSimon Glass
228*eefe3e59SSimon Glass		#address-cells = <1>;
229*eefe3e59SSimon Glass		#size-cells = <1>;
230*eefe3e59SSimon Glass
231*eefe3e59SSimon Glass		ranges = <0x54000000 0x54000000 0x04000000>;
232*eefe3e59SSimon Glass
233*eefe3e59SSimon Glass		/* video-encoding/decoding */
234*eefe3e59SSimon Glass		mpe {
235*eefe3e59SSimon Glass			reg = <0x54040000 0x00040000>;
236*eefe3e59SSimon Glass			interrupts = <0 68 0x04>;
237*eefe3e59SSimon Glass			status = "disabled";
238*eefe3e59SSimon Glass		};
239*eefe3e59SSimon Glass
240*eefe3e59SSimon Glass		/* video input */
241*eefe3e59SSimon Glass		vi {
242*eefe3e59SSimon Glass			reg = <0x54080000 0x00040000>;
243*eefe3e59SSimon Glass			interrupts = <0 69 0x04>;
244*eefe3e59SSimon Glass			status = "disabled";
245*eefe3e59SSimon Glass		};
246*eefe3e59SSimon Glass
247*eefe3e59SSimon Glass		/* EPP */
248*eefe3e59SSimon Glass		epp {
249*eefe3e59SSimon Glass			reg = <0x540c0000 0x00040000>;
250*eefe3e59SSimon Glass			interrupts = <0 70 0x04>;
251*eefe3e59SSimon Glass			status = "disabled";
252*eefe3e59SSimon Glass		};
253*eefe3e59SSimon Glass
254*eefe3e59SSimon Glass		/* ISP */
255*eefe3e59SSimon Glass		isp {
256*eefe3e59SSimon Glass			reg = <0x54100000 0x00040000>;
257*eefe3e59SSimon Glass			interrupts = <0 71 0x04>;
258*eefe3e59SSimon Glass			status = "disabled";
259*eefe3e59SSimon Glass		};
260*eefe3e59SSimon Glass
261*eefe3e59SSimon Glass		/* 2D engine */
262*eefe3e59SSimon Glass		gr2d {
263*eefe3e59SSimon Glass			reg = <0x54140000 0x00040000>;
264*eefe3e59SSimon Glass			interrupts = <0 72 0x04>;
265*eefe3e59SSimon Glass			status = "disabled";
266*eefe3e59SSimon Glass		};
267*eefe3e59SSimon Glass
268*eefe3e59SSimon Glass		/* 3D engine */
269*eefe3e59SSimon Glass		gr3d {
270*eefe3e59SSimon Glass			reg = <0x54180000 0x00040000>;
271*eefe3e59SSimon Glass			status = "disabled";
272*eefe3e59SSimon Glass		};
273*eefe3e59SSimon Glass
274*eefe3e59SSimon Glass		/* display controllers */
275*eefe3e59SSimon Glass		dc@54200000 {
276*eefe3e59SSimon Glass			compatible = "nvidia,tegra20-dc";
277*eefe3e59SSimon Glass			reg = <0x54200000 0x00040000>;
278*eefe3e59SSimon Glass			interrupts = <0 73 0x04>;
279*eefe3e59SSimon Glass			status = "disabled";
280*eefe3e59SSimon Glass
281*eefe3e59SSimon Glass			rgb {
282*eefe3e59SSimon Glass				status = "disabled";
283*eefe3e59SSimon Glass			};
284*eefe3e59SSimon Glass		};
285*eefe3e59SSimon Glass
286*eefe3e59SSimon Glass		dc@54240000 {
287*eefe3e59SSimon Glass			compatible = "nvidia,tegra20-dc";
288*eefe3e59SSimon Glass			reg = <0x54240000 0x00040000>;
289*eefe3e59SSimon Glass			interrupts = <0 74 0x04>;
290*eefe3e59SSimon Glass			status = "disabled";
291*eefe3e59SSimon Glass
292*eefe3e59SSimon Glass			rgb {
293*eefe3e59SSimon Glass				status = "disabled";
294*eefe3e59SSimon Glass			};
295*eefe3e59SSimon Glass		};
296*eefe3e59SSimon Glass
297*eefe3e59SSimon Glass		/* outputs */
298*eefe3e59SSimon Glass		hdmi {
299*eefe3e59SSimon Glass			compatible = "nvidia,tegra20-hdmi";
300*eefe3e59SSimon Glass			reg = <0x54280000 0x00040000>;
301*eefe3e59SSimon Glass			interrupts = <0 75 0x04>;
302*eefe3e59SSimon Glass			status = "disabled";
303*eefe3e59SSimon Glass		};
304*eefe3e59SSimon Glass
305*eefe3e59SSimon Glass		tvo {
306*eefe3e59SSimon Glass			compatible = "nvidia,tegra20-tvo";
307*eefe3e59SSimon Glass			reg = <0x542c0000 0x00040000>;
308*eefe3e59SSimon Glass			interrupts = <0 76 0x04>;
309*eefe3e59SSimon Glass			status = "disabled";
310*eefe3e59SSimon Glass		};
311*eefe3e59SSimon Glass
312*eefe3e59SSimon Glass		dsi {
313*eefe3e59SSimon Glass			compatible = "nvidia,tegra20-dsi";
314*eefe3e59SSimon Glass			reg = <0x54300000 0x00040000>;
315*eefe3e59SSimon Glass			status = "disabled";
316*eefe3e59SSimon Glass		};
317*eefe3e59SSimon Glass	};
318*eefe3e59SSimon Glass
319c3474ef3SSimon Glass};
320