xref: /rk3399_rockchip-uboot/arch/arm/dts/tegra20.dtsi (revision 64e6ec1d4e2f97b6ae03ee158f64f5b0074c214a)
1c3474ef3SSimon Glass/include/ "skeleton.dtsi"
2c3474ef3SSimon Glass
3c3474ef3SSimon Glass/ {
4c3474ef3SSimon Glass	compatible = "nvidia,tegra20";
5c3474ef3SSimon Glass	interrupt-parent = <&intc>;
6c3474ef3SSimon Glass
7eefe3e59SSimon Glass	host1x {
8eefe3e59SSimon Glass		compatible = "nvidia,tegra20-host1x", "simple-bus";
9eefe3e59SSimon Glass		reg = <0x50000000 0x00024000>;
10eefe3e59SSimon Glass		interrupts = <0 65 0x04   /* mpcore syncpt */
11eefe3e59SSimon Glass			      0 67 0x04>; /* mpcore general */
12eefe3e59SSimon Glass		status = "disabled";
13eefe3e59SSimon Glass
14eefe3e59SSimon Glass		#address-cells = <1>;
15eefe3e59SSimon Glass		#size-cells = <1>;
16eefe3e59SSimon Glass
17eefe3e59SSimon Glass		ranges = <0x54000000 0x54000000 0x04000000>;
18eefe3e59SSimon Glass
19eefe3e59SSimon Glass		/* video-encoding/decoding */
20eefe3e59SSimon Glass		mpe {
21eefe3e59SSimon Glass			reg = <0x54040000 0x00040000>;
22eefe3e59SSimon Glass			interrupts = <0 68 0x04>;
23eefe3e59SSimon Glass			status = "disabled";
24eefe3e59SSimon Glass		};
25eefe3e59SSimon Glass
26eefe3e59SSimon Glass		/* video input */
27eefe3e59SSimon Glass		vi {
28eefe3e59SSimon Glass			reg = <0x54080000 0x00040000>;
29eefe3e59SSimon Glass			interrupts = <0 69 0x04>;
30eefe3e59SSimon Glass			status = "disabled";
31eefe3e59SSimon Glass		};
32eefe3e59SSimon Glass
33eefe3e59SSimon Glass		/* EPP */
34eefe3e59SSimon Glass		epp {
35eefe3e59SSimon Glass			reg = <0x540c0000 0x00040000>;
36eefe3e59SSimon Glass			interrupts = <0 70 0x04>;
37eefe3e59SSimon Glass			status = "disabled";
38eefe3e59SSimon Glass		};
39eefe3e59SSimon Glass
40eefe3e59SSimon Glass		/* ISP */
41eefe3e59SSimon Glass		isp {
42eefe3e59SSimon Glass			reg = <0x54100000 0x00040000>;
43eefe3e59SSimon Glass			interrupts = <0 71 0x04>;
44eefe3e59SSimon Glass			status = "disabled";
45eefe3e59SSimon Glass		};
46eefe3e59SSimon Glass
47eefe3e59SSimon Glass		/* 2D engine */
48eefe3e59SSimon Glass		gr2d {
49eefe3e59SSimon Glass			reg = <0x54140000 0x00040000>;
50eefe3e59SSimon Glass			interrupts = <0 72 0x04>;
51eefe3e59SSimon Glass			status = "disabled";
52eefe3e59SSimon Glass		};
53eefe3e59SSimon Glass
54eefe3e59SSimon Glass		/* 3D engine */
55eefe3e59SSimon Glass		gr3d {
56eefe3e59SSimon Glass			reg = <0x54180000 0x00040000>;
57eefe3e59SSimon Glass			status = "disabled";
58eefe3e59SSimon Glass		};
59eefe3e59SSimon Glass
60eefe3e59SSimon Glass		/* display controllers */
61eefe3e59SSimon Glass		dc@54200000 {
62eefe3e59SSimon Glass			compatible = "nvidia,tegra20-dc";
63eefe3e59SSimon Glass			reg = <0x54200000 0x00040000>;
64eefe3e59SSimon Glass			interrupts = <0 73 0x04>;
65eefe3e59SSimon Glass			status = "disabled";
66eefe3e59SSimon Glass
67eefe3e59SSimon Glass			rgb {
68eefe3e59SSimon Glass				status = "disabled";
69eefe3e59SSimon Glass			};
70eefe3e59SSimon Glass		};
71eefe3e59SSimon Glass
72eefe3e59SSimon Glass		dc@54240000 {
73eefe3e59SSimon Glass			compatible = "nvidia,tegra20-dc";
74eefe3e59SSimon Glass			reg = <0x54240000 0x00040000>;
75eefe3e59SSimon Glass			interrupts = <0 74 0x04>;
76eefe3e59SSimon Glass			status = "disabled";
77eefe3e59SSimon Glass
78eefe3e59SSimon Glass			rgb {
79eefe3e59SSimon Glass				status = "disabled";
80eefe3e59SSimon Glass			};
81eefe3e59SSimon Glass		};
82eefe3e59SSimon Glass
83eefe3e59SSimon Glass		/* outputs */
84eefe3e59SSimon Glass		hdmi {
85eefe3e59SSimon Glass			compatible = "nvidia,tegra20-hdmi";
86eefe3e59SSimon Glass			reg = <0x54280000 0x00040000>;
87eefe3e59SSimon Glass			interrupts = <0 75 0x04>;
88eefe3e59SSimon Glass			status = "disabled";
89eefe3e59SSimon Glass		};
90eefe3e59SSimon Glass
91eefe3e59SSimon Glass		tvo {
92eefe3e59SSimon Glass			compatible = "nvidia,tegra20-tvo";
93eefe3e59SSimon Glass			reg = <0x542c0000 0x00040000>;
94eefe3e59SSimon Glass			interrupts = <0 76 0x04>;
95eefe3e59SSimon Glass			status = "disabled";
96eefe3e59SSimon Glass		};
97eefe3e59SSimon Glass
98eefe3e59SSimon Glass		dsi {
99eefe3e59SSimon Glass			compatible = "nvidia,tegra20-dsi";
100eefe3e59SSimon Glass			reg = <0x54300000 0x00040000>;
101eefe3e59SSimon Glass			status = "disabled";
102eefe3e59SSimon Glass		};
103eefe3e59SSimon Glass	};
104eefe3e59SSimon Glass
105b7723f3fSAllen Martin	intc: interrupt-controller@50041000 {
106b7723f3fSAllen Martin		compatible = "nvidia,tegra20-gic";
107b7723f3fSAllen Martin		interrupt-controller;
108b7723f3fSAllen Martin		#interrupt-cells = <1>;
109b7723f3fSAllen Martin		reg = < 0x50041000 0x1000 >,
110b7723f3fSAllen Martin		      < 0x50040100 0x0100 >;
111b7723f3fSAllen Martin	};
112b7723f3fSAllen Martin
113b7723f3fSAllen Martin	tegra_car: clock@60006000 {
114b7723f3fSAllen Martin		compatible = "nvidia,tegra20-car";
115b7723f3fSAllen Martin		reg = <0x60006000 0x1000>;
116b7723f3fSAllen Martin		#clock-cells = <1>;
117b7723f3fSAllen Martin	};
118b7723f3fSAllen Martin
119*64e6ec1dSAllen Martin	apbdma: dma {
120*64e6ec1dSAllen Martin		compatible = "nvidia,tegra20-apbdma";
121*64e6ec1dSAllen Martin		reg = <0x6000a000 0x1200>;
122*64e6ec1dSAllen Martin		interrupts = <0 104 0x04
123*64e6ec1dSAllen Martin			      0 105 0x04
124*64e6ec1dSAllen Martin			      0 106 0x04
125*64e6ec1dSAllen Martin			      0 107 0x04
126*64e6ec1dSAllen Martin			      0 108 0x04
127*64e6ec1dSAllen Martin			      0 109 0x04
128*64e6ec1dSAllen Martin			      0 110 0x04
129*64e6ec1dSAllen Martin			      0 111 0x04
130*64e6ec1dSAllen Martin			      0 112 0x04
131*64e6ec1dSAllen Martin			      0 113 0x04
132*64e6ec1dSAllen Martin			      0 114 0x04
133*64e6ec1dSAllen Martin			      0 115 0x04
134*64e6ec1dSAllen Martin			      0 116 0x04
135*64e6ec1dSAllen Martin			      0 117 0x04
136*64e6ec1dSAllen Martin			      0 118 0x04
137*64e6ec1dSAllen Martin			      0 119 0x04>;
138*64e6ec1dSAllen Martin	};
139*64e6ec1dSAllen Martin
140b7723f3fSAllen Martin	gpio: gpio@6000d000 {
141b7723f3fSAllen Martin		compatible = "nvidia,tegra20-gpio";
142b7723f3fSAllen Martin		reg = < 0x6000d000 0x1000 >;
143b7723f3fSAllen Martin		interrupts = < 64 65 66 67 87 119 121 >;
144b7723f3fSAllen Martin		#gpio-cells = <2>;
145b7723f3fSAllen Martin		gpio-controller;
146b7723f3fSAllen Martin	};
147b7723f3fSAllen Martin
148b7723f3fSAllen Martin	pinmux: pinmux@70000000 {
149b7723f3fSAllen Martin		compatible = "nvidia,tegra20-pinmux";
150b7723f3fSAllen Martin		reg = < 0x70000014 0x10    /* Tri-state registers */
151b7723f3fSAllen Martin			0x70000080 0x20    /* Mux registers */
152b7723f3fSAllen Martin			0x700000a0 0x14    /* Pull-up/down registers */
153b7723f3fSAllen Martin			0x70000868 0xa8 >; /* Pad control registers */
154b7723f3fSAllen Martin	};
155b7723f3fSAllen Martin
156b7723f3fSAllen Martin	das@70000c00 {
157b7723f3fSAllen Martin		#address-cells = <1>;
158b7723f3fSAllen Martin		#size-cells = <0>;
159b7723f3fSAllen Martin		compatible = "nvidia,tegra20-das";
160b7723f3fSAllen Martin		reg = <0x70000c00 0x80>;
161b7723f3fSAllen Martin	};
162b7723f3fSAllen Martin
163b7723f3fSAllen Martin	i2s@70002800 {
164b7723f3fSAllen Martin		#address-cells = <1>;
165b7723f3fSAllen Martin		#size-cells = <0>;
166b7723f3fSAllen Martin		compatible = "nvidia,tegra20-i2s";
167b7723f3fSAllen Martin		reg = <0x70002800 0x200>;
168b7723f3fSAllen Martin		interrupts = < 45 >;
169b7723f3fSAllen Martin		dma-channel = < 2 >;
170b7723f3fSAllen Martin	};
171b7723f3fSAllen Martin
172b7723f3fSAllen Martin	i2s@70002a00 {
173b7723f3fSAllen Martin		#address-cells = <1>;
174b7723f3fSAllen Martin		#size-cells = <0>;
175b7723f3fSAllen Martin		compatible = "nvidia,tegra20-i2s";
176b7723f3fSAllen Martin		reg = <0x70002a00 0x200>;
177b7723f3fSAllen Martin		interrupts = < 35 >;
178b7723f3fSAllen Martin		dma-channel = < 1 >;
179b7723f3fSAllen Martin	};
180b7723f3fSAllen Martin
181b7723f3fSAllen Martin	serial@70006000 {
182b7723f3fSAllen Martin		compatible = "nvidia,tegra20-uart";
183b7723f3fSAllen Martin		reg = <0x70006000 0x40>;
184b7723f3fSAllen Martin		reg-shift = <2>;
185b7723f3fSAllen Martin		interrupts = < 68 >;
186b7723f3fSAllen Martin	};
187b7723f3fSAllen Martin
188b7723f3fSAllen Martin	serial@70006040 {
189b7723f3fSAllen Martin		compatible = "nvidia,tegra20-uart";
190b7723f3fSAllen Martin		reg = <0x70006040 0x40>;
191b7723f3fSAllen Martin		reg-shift = <2>;
192b7723f3fSAllen Martin		interrupts = < 69 >;
193b7723f3fSAllen Martin	};
194b7723f3fSAllen Martin
195b7723f3fSAllen Martin	serial@70006200 {
196b7723f3fSAllen Martin		compatible = "nvidia,tegra20-uart";
197b7723f3fSAllen Martin		reg = <0x70006200 0x100>;
198b7723f3fSAllen Martin		reg-shift = <2>;
199b7723f3fSAllen Martin		interrupts = < 78 >;
200b7723f3fSAllen Martin	};
201b7723f3fSAllen Martin
202b7723f3fSAllen Martin	serial@70006300 {
203b7723f3fSAllen Martin		compatible = "nvidia,tegra20-uart";
204b7723f3fSAllen Martin		reg = <0x70006300 0x100>;
205b7723f3fSAllen Martin		reg-shift = <2>;
206b7723f3fSAllen Martin		interrupts = < 122 >;
207b7723f3fSAllen Martin	};
208b7723f3fSAllen Martin
209b7723f3fSAllen Martin	serial@70006400 {
210b7723f3fSAllen Martin		compatible = "nvidia,tegra20-uart";
211b7723f3fSAllen Martin		reg = <0x70006400 0x100>;
212b7723f3fSAllen Martin		reg-shift = <2>;
213b7723f3fSAllen Martin		interrupts = < 123 >;
214b7723f3fSAllen Martin	};
215b7723f3fSAllen Martin
216b7723f3fSAllen Martin	nand: nand-controller@70008000 {
217b7723f3fSAllen Martin		#address-cells = <1>;
218b7723f3fSAllen Martin		#size-cells = <0>;
219b7723f3fSAllen Martin		compatible = "nvidia,tegra20-nand";
220b7723f3fSAllen Martin		reg = <0x70008000 0x100>;
221b7723f3fSAllen Martin	};
222b7723f3fSAllen Martin
223b7723f3fSAllen Martin	pwm: pwm@7000a000 {
224b7723f3fSAllen Martin		compatible = "nvidia,tegra20-pwm";
225b7723f3fSAllen Martin		reg = <0x7000a000 0x100>;
226b7723f3fSAllen Martin		#pwm-cells = <2>;
227b7723f3fSAllen Martin	};
228b7723f3fSAllen Martin
229b7723f3fSAllen Martin	i2c@7000c000 {
230b7723f3fSAllen Martin		#address-cells = <1>;
231b7723f3fSAllen Martin		#size-cells = <0>;
232b7723f3fSAllen Martin		compatible = "nvidia,tegra20-i2c";
233b7723f3fSAllen Martin		reg = <0x7000C000 0x100>;
234b7723f3fSAllen Martin		interrupts = < 70 >;
235b7723f3fSAllen Martin		/* PERIPH_ID_I2C1, PLL_P_OUT3 */
236b7723f3fSAllen Martin		clocks = <&tegra_car 12>, <&tegra_car 124>;
237b7723f3fSAllen Martin	};
238b7723f3fSAllen Martin
239b7723f3fSAllen Martin	i2c@7000c400 {
240b7723f3fSAllen Martin		#address-cells = <1>;
241b7723f3fSAllen Martin		#size-cells = <0>;
242b7723f3fSAllen Martin		compatible = "nvidia,tegra20-i2c";
243b7723f3fSAllen Martin		reg = <0x7000C400 0x100>;
244b7723f3fSAllen Martin		interrupts = < 116 >;
245b7723f3fSAllen Martin		/* PERIPH_ID_I2C2, PLL_P_OUT3 */
246b7723f3fSAllen Martin		clocks = <&tegra_car 54>, <&tegra_car 124>;
247b7723f3fSAllen Martin	};
248b7723f3fSAllen Martin
249b7723f3fSAllen Martin	i2c@7000c500 {
250b7723f3fSAllen Martin		#address-cells = <1>;
251b7723f3fSAllen Martin		#size-cells = <0>;
252b7723f3fSAllen Martin		compatible = "nvidia,tegra20-i2c";
253b7723f3fSAllen Martin		reg = <0x7000C500 0x100>;
254b7723f3fSAllen Martin		interrupts = < 124 >;
255b7723f3fSAllen Martin		/* PERIPH_ID_I2C3, PLL_P_OUT3 */
256b7723f3fSAllen Martin		clocks = <&tegra_car 67>, <&tegra_car 124>;
257b7723f3fSAllen Martin	};
258b7723f3fSAllen Martin
259b7723f3fSAllen Martin	i2c@7000d000 {
260b7723f3fSAllen Martin		#address-cells = <1>;
261b7723f3fSAllen Martin		#size-cells = <0>;
262b7723f3fSAllen Martin		compatible = "nvidia,tegra20-i2c-dvc";
263b7723f3fSAllen Martin		reg = <0x7000D000 0x200>;
264b7723f3fSAllen Martin		interrupts = < 85 >;
265b7723f3fSAllen Martin		/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
266b7723f3fSAllen Martin		clocks = <&tegra_car 47>, <&tegra_car 124>;
267b7723f3fSAllen Martin	};
268b7723f3fSAllen Martin
269b7723f3fSAllen Martin	kbc@7000e200 {
270b7723f3fSAllen Martin		compatible = "nvidia,tegra20-kbc";
271b7723f3fSAllen Martin		reg = <0x7000e200 0x0078>;
272b7723f3fSAllen Martin	};
273b7723f3fSAllen Martin
274b7723f3fSAllen Martin	emc@7000f400 {
275b7723f3fSAllen Martin		#address-cells = < 1 >;
276b7723f3fSAllen Martin		#size-cells = < 0 >;
277b7723f3fSAllen Martin		compatible = "nvidia,tegra20-emc";
278b7723f3fSAllen Martin		reg = <0x7000f400 0x200>;
279b7723f3fSAllen Martin	};
280b7723f3fSAllen Martin
281b7723f3fSAllen Martin	usb@c5000000 {
282b7723f3fSAllen Martin		compatible = "nvidia,tegra20-ehci", "usb-ehci";
283b7723f3fSAllen Martin		reg = <0xc5000000 0x4000>;
284b7723f3fSAllen Martin		interrupts = < 52 >;
285b7723f3fSAllen Martin		phy_type = "utmi";
286b7723f3fSAllen Martin		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
287b7723f3fSAllen Martin		nvidia,has-legacy-mode;
288b7723f3fSAllen Martin	};
289b7723f3fSAllen Martin
290b7723f3fSAllen Martin	usb@c5004000 {
291b7723f3fSAllen Martin		compatible = "nvidia,tegra20-ehci", "usb-ehci";
292b7723f3fSAllen Martin		reg = <0xc5004000 0x4000>;
293b7723f3fSAllen Martin		interrupts = < 53 >;
294b7723f3fSAllen Martin		phy_type = "ulpi";
295b7723f3fSAllen Martin		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
296b7723f3fSAllen Martin	};
297b7723f3fSAllen Martin
298b7723f3fSAllen Martin	usb@c5008000 {
299b7723f3fSAllen Martin		compatible = "nvidia,tegra20-ehci", "usb-ehci";
300b7723f3fSAllen Martin		reg = <0xc5008000 0x4000>;
301b7723f3fSAllen Martin		interrupts = < 129 >;
302b7723f3fSAllen Martin		phy_type = "utmi";
303b7723f3fSAllen Martin		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
304b7723f3fSAllen Martin	};
305b7723f3fSAllen Martin
306b7723f3fSAllen Martin	sdhci@c8000000 {
307b7723f3fSAllen Martin		compatible = "nvidia,tegra20-sdhci";
308b7723f3fSAllen Martin		reg = <0xc8000000 0x200>;
309b7723f3fSAllen Martin		interrupts = < 46 >;
310b7723f3fSAllen Martin	};
311b7723f3fSAllen Martin
312b7723f3fSAllen Martin	sdhci@c8000200 {
313b7723f3fSAllen Martin		compatible = "nvidia,tegra20-sdhci";
314b7723f3fSAllen Martin		reg = <0xc8000200 0x200>;
315b7723f3fSAllen Martin		interrupts = < 47 >;
316b7723f3fSAllen Martin	};
317b7723f3fSAllen Martin
318b7723f3fSAllen Martin	sdhci@c8000400 {
319b7723f3fSAllen Martin		compatible = "nvidia,tegra20-sdhci";
320b7723f3fSAllen Martin		reg = <0xc8000400 0x200>;
321b7723f3fSAllen Martin		interrupts = < 51 >;
322b7723f3fSAllen Martin	};
323b7723f3fSAllen Martin
324b7723f3fSAllen Martin	sdhci@c8000600 {
325b7723f3fSAllen Martin		compatible = "nvidia,tegra20-sdhci";
326b7723f3fSAllen Martin		reg = <0xc8000600 0x200>;
327b7723f3fSAllen Martin		interrupts = < 63 >;
328b7723f3fSAllen Martin	};
329c3474ef3SSimon Glass};
330