1#include "skeleton.dtsi" 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/power/tegra186-powergate.h> 7#include <dt-bindings/reset/tegra186-reset.h> 8 9/ { 10 compatible = "nvidia,tegra186"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 gpio_main: gpio@2200000 { 16 compatible = "nvidia,tegra186-gpio"; 17 reg-names = "security", "gpio"; 18 reg = 19 <0x0 0x2200000 0x0 0x10000>, 20 <0x0 0x2210000 0x0 0x10000>; 21 interrupts = 22 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 26 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 28 gpio-controller; 29 #gpio-cells = <2>; 30 interrupt-controller; 31 #interrupt-cells = <2>; 32 }; 33 34 uarta: serial@3100000 { 35 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 36 reg = <0x0 0x03100000 0x0 0x10000>; 37 reg-shift = <2>; 38 status = "disabled"; 39 }; 40 41 sdhci@3400000 { 42 compatible = "nvidia,tegra186-sdhci"; 43 reg = <0x0 0x03400000 0x0 0x200>; 44 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 45 reset-names = "sdmmc"; 46 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 47 clock-names = "sdmmc"; 48 interrupts = <GIC_SPI 62 0x04>; 49 status = "disabled"; 50 }; 51 52 sdhci@3460000 { 53 compatible = "nvidia,tegra186-sdhci"; 54 reg = <0x0 0x03460000 0x0 0x200>; 55 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 56 reset-names = "sdmmc"; 57 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 58 clock-names = "sdmmc"; 59 interrupts = <GIC_SPI 31 0x04>; 60 status = "disabled"; 61 }; 62 63 gic: interrupt-controller@3881000 { 64 compatible = "arm,gic-400"; 65 #interrupt-cells = <3>; 66 interrupt-controller; 67 reg = <0x0 0x3881000 0x0 0x1000>, 68 <0x0 0x3882000 0x0 0x2000>, 69 <0x0 0x3884000 0x0 0x2000>, 70 <0x0 0x3886000 0x0 0x2000>; 71 interrupts = <GIC_PPI 9 72 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 73 interrupt-parent = <&gic>; 74 }; 75 76 hsp: hsp@3c00000 { 77 compatible = "nvidia,tegra186-hsp"; 78 reg = <0x0 0x03c00000 0x0 0xa0000>; 79 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 80 interrupt-names = "doorbell"; 81 #mbox-cells = <2>; 82 }; 83 84 gpio_aon: gpio@c2f0000 { 85 compatible = "nvidia,tegra186-gpio-aon"; 86 reg-names = "security", "gpio"; 87 reg = 88 <0x0 0xc2f0000 0x0 0x1000>, 89 <0x0 0xc2f1000 0x0 0x1000>; 90 interrupts = 91 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 interrupt-controller; 95 #interrupt-cells = <2>; 96 }; 97 98 pcie-controller@10003000 { 99 compatible = "nvidia,tegra186-pcie"; 100 device_type = "pci"; 101 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 102 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 103 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 104 reg-names = "pads", "afi", "cs"; 105 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 106 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ 107 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ 108 interrupt-names = "intr", "msi", "wake"; 109 110 #interrupt-cells = <1>; 111 interrupt-map-mask = <0 0 0 0>; 112 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 113 114 bus-range = <0x00 0xff>; 115 #address-cells = <3>; 116 #size-cells = <2>; 117 118 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 119 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 120 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 121 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 122 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ 123 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 124 125 clocks = <&bpmp TEGRA186_CLK_PCIE>, 126 <&bpmp TEGRA186_CLK_AFI>; 127 clock-names = "pex", "afi"; 128 resets = <&bpmp TEGRA186_RESET_PCIE>, 129 <&bpmp TEGRA186_RESET_AFI>, 130 <&bpmp TEGRA186_RESET_PCIEXCLK>; 131 reset-names = "pex", "afi", "pcie_x"; 132 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 133 status = "disabled"; 134 135 pci@1,0 { 136 device_type = "pci"; 137 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 138 reg = <0x000800 0 0 0 0>; 139 status = "disabled"; 140 141 #address-cells = <3>; 142 #size-cells = <2>; 143 ranges; 144 145 nvidia,num-lanes = <2>; 146 }; 147 148 pci@2,0 { 149 device_type = "pci"; 150 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 151 reg = <0x001000 0 0 0 0>; 152 status = "disabled"; 153 154 #address-cells = <3>; 155 #size-cells = <2>; 156 ranges; 157 158 nvidia,num-lanes = <1>; 159 }; 160 161 pci@3,0 { 162 device_type = "pci"; 163 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 164 reg = <0x001800 0 0 0 0>; 165 status = "disabled"; 166 167 #address-cells = <3>; 168 #size-cells = <2>; 169 ranges; 170 171 nvidia,num-lanes = <1>; 172 }; 173 }; 174 175 sysram@30000000 { 176 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 177 reg = <0x0 0x30000000 0x0 0x50000>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 181 182 sysram_cpu_bpmp_tx: shmem@4e000 { 183 compatible = "nvidia,tegra186-bpmp-shmem"; 184 reg = <0x0 0x4e000 0x0 0x1000>; 185 }; 186 187 sysram_cpu_bpmp_rx: shmem@4f000 { 188 compatible = "nvidia,tegra186-bpmp-shmem"; 189 reg = <0x0 0x4f000 0x0 0x1000>; 190 }; 191 }; 192 193 bpmp: bpmp { 194 compatible = "nvidia,tegra186-bpmp"; 195 mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; 196 /* 197 * In theory, these references, and the configuration in the 198 * node these reference point at, are board-specific, since 199 * they depend on the BCT's memory carve-out setup, the 200 * firmware that's actually loaded onto the BPMP, etc. However, 201 * in practice, all boards are likely to use identical values. 202 */ 203 shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; 204 #clock-cells = <1>; 205 #power-domain-cells = <1>; 206 #reset-cells = <1>; 207 208 bpmp_i2c: i2c { 209 compatible = "nvidia,tegra186-bpmp-i2c"; 210 nvidia,bpmp = <&bpmp>; 211 nvidia,bpmp-bus-id = <5>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 status = "disabled"; 215 }; 216 }; 217}; 218