xref: /rk3399_rockchip-uboot/arch/arm/dts/tegra186.dtsi (revision 729c2db7a977c59ea35bbc56fb1633c17342b3c5)
1c7ba99c8SStephen Warren#include "skeleton.dtsi"
20388634aSStephen Warren#include <dt-bindings/gpio/tegra186-gpio.h>
3c7ba99c8SStephen Warren#include <dt-bindings/interrupt-controller/arm-gic.h>
4*729c2db7SStephen Warren#include <dt-bindings/mailbox/tegra186-hsp.h>
5c7ba99c8SStephen Warren
6c7ba99c8SStephen Warren/ {
7c7ba99c8SStephen Warren	compatible = "nvidia,tegra186";
8c7ba99c8SStephen Warren	#address-cells = <2>;
9c7ba99c8SStephen Warren	#size-cells = <2>;
10c7ba99c8SStephen Warren
11c7ba99c8SStephen Warren	gpio@2200000 {
12c7ba99c8SStephen Warren		compatible = "nvidia,tegra186-gpio";
13c7ba99c8SStephen Warren		reg-names = "security", "gpio";
14c7ba99c8SStephen Warren		reg =
15c7ba99c8SStephen Warren			<0x0 0x2200000 0x0 0x10000>,
16c7ba99c8SStephen Warren			<0x0 0x2210000 0x0 0x10000>;
17c7ba99c8SStephen Warren		interrupts =
18c7ba99c8SStephen Warren			<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
19c7ba99c8SStephen Warren			<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
20c7ba99c8SStephen Warren			<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
21c7ba99c8SStephen Warren			<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
22c7ba99c8SStephen Warren			<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
23c7ba99c8SStephen Warren			<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
24c7ba99c8SStephen Warren		gpio-controller;
25c7ba99c8SStephen Warren		#gpio-cells = <2>;
26c7ba99c8SStephen Warren		interrupt-controller;
27c7ba99c8SStephen Warren		#interrupt-cells = <2>;
28c7ba99c8SStephen Warren	};
29c7ba99c8SStephen Warren
30c7ba99c8SStephen Warren	uarta: serial@3100000 {
31c7ba99c8SStephen Warren		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
32c7ba99c8SStephen Warren		reg = <0x0 0x03100000 0x0 0x10000>;
33c7ba99c8SStephen Warren		reg-shift = <2>;
34c7ba99c8SStephen Warren		status = "disabled";
35c7ba99c8SStephen Warren	};
36c7ba99c8SStephen Warren
37c7ba99c8SStephen Warren	sdhci@3460000 {
38c7ba99c8SStephen Warren		compatible = "nvidia,tegra186-sdhci";
39c7ba99c8SStephen Warren		reg = <0x0 0x03460000 0x0 0x200>;
40c7ba99c8SStephen Warren		interrupts = <GIC_SPI 31 0x04>;
41c7ba99c8SStephen Warren		status = "disabled";
42c7ba99c8SStephen Warren	};
43c7ba99c8SStephen Warren
440f67e239SStephen Warren	hsp: hsp@3c00000 {
450f67e239SStephen Warren		compatible = "nvidia,tegra186-hsp";
460f67e239SStephen Warren		reg = <0x0 0x03c00000 0x0 0xa0000>;
470f67e239SStephen Warren		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
48*729c2db7SStephen Warren		interrupt-names = "doorbell";
49*729c2db7SStephen Warren		#mbox-cells = <2>;
500f67e239SStephen Warren	};
510f67e239SStephen Warren
52c7ba99c8SStephen Warren	gpio@c2f0000 {
53c7ba99c8SStephen Warren		compatible = "nvidia,tegra186-gpio-aon";
54c7ba99c8SStephen Warren		reg-names = "security", "gpio";
55c7ba99c8SStephen Warren		reg =
56c7ba99c8SStephen Warren			<0x0 0xc2f0000 0x0 0x1000>,
57c7ba99c8SStephen Warren			<0x0 0xc2f1000 0x0 0x1000>;
58c7ba99c8SStephen Warren		interrupts =
59c7ba99c8SStephen Warren			<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
60c7ba99c8SStephen Warren		gpio-controller;
61c7ba99c8SStephen Warren		#gpio-cells = <2>;
62c7ba99c8SStephen Warren		interrupt-controller;
63c7ba99c8SStephen Warren		#interrupt-cells = <2>;
64c7ba99c8SStephen Warren	};
65c7ba99c8SStephen Warren};
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