1#include <dt-bindings/clock/tegra124-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/pinctrl/pinctrl-tegra.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 6 7#include "skeleton.dtsi" 8 9/ { 10 compatible = "nvidia,tegra124"; 11 12 tegra_car: clock@60006000 { 13 compatible = "nvidia,tegra124-car"; 14 reg = <0x60006000 0x1000>; 15 #clock-cells = <1>; 16 }; 17 18 apbdma: dma@60020000 { 19 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 20 reg = <0x60020000 0x1400>; 21 interrupts = <0 104 0x04 22 0 105 0x04 23 0 106 0x04 24 0 107 0x04 25 0 108 0x04 26 0 109 0x04 27 0 110 0x04 28 0 111 0x04 29 0 112 0x04 30 0 113 0x04 31 0 114 0x04 32 0 115 0x04 33 0 116 0x04 34 0 117 0x04 35 0 118 0x04 36 0 119 0x04 37 0 128 0x04 38 0 129 0x04 39 0 130 0x04 40 0 131 0x04 41 0 132 0x04 42 0 133 0x04 43 0 134 0x04 44 0 135 0x04 45 0 136 0x04 46 0 137 0x04 47 0 138 0x04 48 0 139 0x04 49 0 140 0x04 50 0 141 0x04 51 0 142 0x04 52 0 143 0x04>; 53 }; 54 55 gpio: gpio@6000d000 { 56 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 57 reg = <0x6000d000 0x1000>; 58 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 66 #gpio-cells = <2>; 67 gpio-controller; 68 #interrupt-cells = <2>; 69 interrupt-controller; 70 }; 71 72 i2c@7000c000 { 73 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 74 reg = <0x7000c000 0x100>; 75 interrupts = <0 38 0x04>; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 clocks = <&tegra_car 12>; 79 status = "disabled"; 80 }; 81 82 i2c@7000c400 { 83 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 84 reg = <0x7000c400 0x100>; 85 interrupts = <0 84 0x04>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 clocks = <&tegra_car 54>; 89 status = "disabled"; 90 }; 91 92 i2c@7000c500 { 93 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 94 reg = <0x7000c500 0x100>; 95 interrupts = <0 92 0x04>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 clocks = <&tegra_car 67>; 99 status = "disabled"; 100 }; 101 102 i2c@7000c700 { 103 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 104 reg = <0x7000c700 0x100>; 105 interrupts = <0 120 0x04>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 clocks = <&tegra_car 103>; 109 status = "disabled"; 110 }; 111 112 i2c@7000d000 { 113 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 114 reg = <0x7000d000 0x100>; 115 interrupts = <0 53 0x04>; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 clocks = <&tegra_car 47>; 119 status = "disabled"; 120 }; 121 122 i2c@7000d100 { 123 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 124 reg = <0x7000d100 0x100>; 125 interrupts = <0 53 0x04>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&tegra_car 47>; 129 status = "disabled"; 130 }; 131 132 uarta: serial@70006000 { 133 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 134 reg = <0x70006000 0x40>; 135 reg-shift = <2>; 136 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 138 resets = <&tegra_car 6>; 139 reset-names = "serial"; 140 dmas = <&apbdma 8>, <&apbdma 8>; 141 dma-names = "rx", "tx"; 142 status = "disabled"; 143 }; 144 145 uartb: serial@70006040 { 146 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 147 reg = <0x70006040 0x40>; 148 reg-shift = <2>; 149 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 151 resets = <&tegra_car 7>; 152 reset-names = "serial"; 153 dmas = <&apbdma 9>, <&apbdma 9>; 154 dma-names = "rx", "tx"; 155 status = "disabled"; 156 }; 157 158 uartc: serial@70006200 { 159 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 160 reg = <0x70006200 0x40>; 161 reg-shift = <2>; 162 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 164 resets = <&tegra_car 55>; 165 reset-names = "serial"; 166 dmas = <&apbdma 10>, <&apbdma 10>; 167 dma-names = "rx", "tx"; 168 status = "disabled"; 169 }; 170 171 uartd: serial@70006300 { 172 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 173 reg = <0x70006300 0x40>; 174 reg-shift = <2>; 175 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 177 resets = <&tegra_car 65>; 178 reset-names = "serial"; 179 dmas = <&apbdma 19>, <&apbdma 19>; 180 dma-names = "rx", "tx"; 181 status = "disabled"; 182 }; 183 184 uarte: serial@70006400 { 185 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 186 reg = <0x70006400 0x40>; 187 reg-shift = <2>; 188 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&tegra_car TEGRA124_CLK_UARTE>; 190 resets = <&tegra_car 66>; 191 reset-names = "serial"; 192 dmas = <&apbdma 20>, <&apbdma 20>; 193 dma-names = "rx", "tx"; 194 status = "disabled"; 195 }; 196 197 pwm: pwm@7000a000 { 198 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 199 reg = <0x7000a000 0x100>; 200 #pwm-cells = <2>; 201 clocks = <&tegra_car TEGRA124_CLK_PWM>; 202 resets = <&tegra_car 17>; 203 reset-names = "pwm"; 204 status = "disabled"; 205 }; 206 207 spi@7000d400 { 208 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 209 reg = <0x7000d400 0x200>; 210 interrupts = <0 59 0x04>; 211 nvidia,dma-request-selector = <&apbdma 15>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 status = "disabled"; 215 clocks = <&tegra_car 41>; 216 }; 217 218 spi@7000d600 { 219 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 220 reg = <0x7000d600 0x200>; 221 interrupts = <0 82 0x04>; 222 nvidia,dma-request-selector = <&apbdma 16>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 status = "disabled"; 226 clocks = <&tegra_car 44>; 227 }; 228 229 spi@7000d800 { 230 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 231 reg = <0x7000d800 0x200>; 232 interrupts = <0 83 0x04>; 233 nvidia,dma-request-selector = <&apbdma 17>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 status = "disabled"; 237 clocks = <&tegra_car 46>; 238 }; 239 240 spi@7000da00 { 241 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 242 reg = <0x7000da00 0x200>; 243 interrupts = <0 93 0x04>; 244 nvidia,dma-request-selector = <&apbdma 18>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 status = "disabled"; 248 clocks = <&tegra_car 68>; 249 }; 250 251 spi@7000dc00 { 252 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 253 reg = <0x7000dc00 0x200>; 254 interrupts = <0 94 0x04>; 255 nvidia,dma-request-selector = <&apbdma 27>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 status = "disabled"; 259 clocks = <&tegra_car 104>; 260 }; 261 262 spi@7000de00 { 263 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 264 reg = <0x7000de00 0x200>; 265 interrupts = <0 79 0x04>; 266 nvidia,dma-request-selector = <&apbdma 28>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 status = "disabled"; 270 clocks = <&tegra_car 105>; 271 }; 272 273 padctl: padctl@7009f000 { 274 compatible = "nvidia,tegra124-xusb-padctl"; 275 reg = <0x7009f000 0x1000>; 276 resets = <&tegra_car 142>; 277 reset-names = "padctl"; 278 279 #phy-cells = <1>; 280 }; 281 282 sdhci@700b0000 { 283 compatible = "nvidia,tegra124-sdhci"; 284 reg = <0x700b0000 0x200>; 285 interrupts = <0 14 0x04>; 286 clocks = <&tegra_car 14>; 287 status = "disabled"; 288 }; 289 290 sdhci@700b0200 { 291 compatible = "nvidia,tegra124-sdhci"; 292 reg = <0x700b0200 0x200>; 293 interrupts = <0 15 0x04>; 294 clocks = <&tegra_car 9>; 295 status = "disabled"; 296 }; 297 298 sdhci@700b0400 { 299 compatible = "nvidia,tegra124-sdhci"; 300 reg = <0x700b0400 0x200>; 301 interrupts = <0 19 0x04>; 302 clocks = <&tegra_car 69>; 303 status = "disabled"; 304 }; 305 306 sdhci@700b0600 { 307 compatible = "nvidia,tegra124-sdhci"; 308 reg = <0x700b0600 0x200>; 309 interrupts = <0 31 0x04>; 310 clocks = <&tegra_car 15>; 311 status = "disabled"; 312 }; 313 314 ahub@70300000 { 315 compatible = "nvidia,tegra124-ahub"; 316 reg = <0x70300000 0x200>, 317 <0x70300800 0x800>, 318 <0x70300200 0x600>; 319 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 321 <&tegra_car TEGRA124_CLK_APBIF>; 322 clock-names = "d_audio", "apbif"; 323 resets = <&tegra_car 106>, /* d_audio */ 324 <&tegra_car 107>, /* apbif */ 325 <&tegra_car 30>, /* i2s0 */ 326 <&tegra_car 11>, /* i2s1 */ 327 <&tegra_car 18>, /* i2s2 */ 328 <&tegra_car 101>, /* i2s3 */ 329 <&tegra_car 102>, /* i2s4 */ 330 <&tegra_car 108>, /* dam0 */ 331 <&tegra_car 109>, /* dam1 */ 332 <&tegra_car 110>, /* dam2 */ 333 <&tegra_car 10>, /* spdif */ 334 <&tegra_car 153>, /* amx */ 335 <&tegra_car 185>, /* amx1 */ 336 <&tegra_car 154>, /* adx */ 337 <&tegra_car 180>, /* adx1 */ 338 <&tegra_car 186>, /* afc0 */ 339 <&tegra_car 187>, /* afc1 */ 340 <&tegra_car 188>, /* afc2 */ 341 <&tegra_car 189>, /* afc3 */ 342 <&tegra_car 190>, /* afc4 */ 343 <&tegra_car 191>; /* afc5 */ 344 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 345 "i2s3", "i2s4", "dam0", "dam1", "dam2", 346 "spdif", "amx", "amx1", "adx", "adx1", 347 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 348 dmas = <&apbdma 1>, <&apbdma 1>, 349 <&apbdma 2>, <&apbdma 2>, 350 <&apbdma 3>, <&apbdma 3>, 351 <&apbdma 4>, <&apbdma 4>, 352 <&apbdma 6>, <&apbdma 6>, 353 <&apbdma 7>, <&apbdma 7>, 354 <&apbdma 12>, <&apbdma 12>, 355 <&apbdma 13>, <&apbdma 13>, 356 <&apbdma 14>, <&apbdma 14>, 357 <&apbdma 29>, <&apbdma 29>; 358 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 359 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 360 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 361 "rx9", "tx9"; 362 ranges; 363 #address-cells = <1>; 364 #size-cells = <1>; 365 366 tegra_i2s0: i2s@70301000 { 367 compatible = "nvidia,tegra124-i2s"; 368 reg = <0x70301000 0x100>; 369 nvidia,ahub-cif-ids = <4 4>; 370 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 371 resets = <&tegra_car 30>; 372 reset-names = "i2s"; 373 status = "disabled"; 374 }; 375 376 tegra_i2s1: i2s@70301100 { 377 compatible = "nvidia,tegra124-i2s"; 378 reg = <0x70301100 0x100>; 379 nvidia,ahub-cif-ids = <5 5>; 380 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 381 resets = <&tegra_car 11>; 382 reset-names = "i2s"; 383 status = "disabled"; 384 }; 385 386 tegra_i2s2: i2s@70301200 { 387 compatible = "nvidia,tegra124-i2s"; 388 reg = <0x70301200 0x100>; 389 nvidia,ahub-cif-ids = <6 6>; 390 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 391 resets = <&tegra_car 18>; 392 reset-names = "i2s"; 393 status = "disabled"; 394 }; 395 396 tegra_i2s3: i2s@70301300 { 397 compatible = "nvidia,tegra124-i2s"; 398 reg = <0x70301300 0x100>; 399 nvidia,ahub-cif-ids = <7 7>; 400 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 401 resets = <&tegra_car 101>; 402 reset-names = "i2s"; 403 status = "disabled"; 404 }; 405 406 tegra_i2s4: i2s@70301400 { 407 compatible = "nvidia,tegra124-i2s"; 408 reg = <0x70301400 0x100>; 409 nvidia,ahub-cif-ids = <8 8>; 410 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 411 resets = <&tegra_car 102>; 412 reset-names = "i2s"; 413 status = "disabled"; 414 }; 415 }; 416 417 usb@7d000000 { 418 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 419 reg = <0x7d000000 0x4000>; 420 interrupts = < 52 >; 421 phy_type = "utmi"; 422 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ 423 status = "disabled"; 424 }; 425 426 usb@7d004000 { 427 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 428 reg = <0x7d004000 0x4000>; 429 interrupts = < 53 >; 430 phy_type = "hsic"; 431 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ 432 status = "disabled"; 433 }; 434 435 usb@7d008000 { 436 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 437 reg = <0x7d008000 0x4000>; 438 interrupts = < 129 >; 439 phy_type = "utmi"; 440 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ 441 status = "disabled"; 442 }; 443}; 444