xref: /rk3399_rockchip-uboot/arch/arm/dts/stv0991.dts (revision 90a2f7171182f3b96c28b2dcff67b02a3164cdb1)
1/dts-v1/;
2
3/ {
4	model = "ST STV0991 application board";
5	compatible = "st,stv0991";
6	#address-cells = <1>;
7	#size-cells = <1>;
8
9	chosen {
10		stdout-path = &uart0;
11	};
12
13	memory {
14		device_type="memory";
15		reg = <0x0 0x198000>;
16	};
17
18	uart0: serial@0x80406000 {
19		compatible = "arm,pl011", "arm,primecell";
20		reg = <0x80406000 0x1000>;
21		clock = <2700000>;
22	};
23
24	aliases {
25		spi0 = "/spi@80203000";		/* QSPI */
26	};
27
28	qspi: spi@80203000 {
29			compatible = "cadence,qspi";
30			#address-cells = <1>;
31			#size-cells = <0>;
32			reg = <0x80203000 0x100>,
33				<0x40000000 0x1000000>;
34			clocks = <3750000>;
35			ext-decoder = <0>; /* external decoder */
36			num-cs = <4>;
37			fifo-depth = <256>;
38			sram-size = <256>;
39			bus-num = <0>;
40			status = "okay";
41
42			flash0: n25q32@0 {
43				#address-cells = <1>;
44				#size-cells = <1>;
45				compatible = "spi-flash";
46				reg = <0>;		/* chip select */
47				spi-max-frequency = <50000000>;
48				m25p,fast-read;
49				page-size = <256>;
50				block-size = <16>; 	/* 2^16, 64KB */
51				read-delay = <4>;	/* delay value in read data capture register */
52				tshsl-ns = <50>;
53				tsd2d-ns = <50>;
54				tchsh-ns = <4>;
55				tslch-ns = <4>;
56			};
57	};
58};
59