1/* 2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> 3 * 4 * Based on: 5 * stm32f429.dtsi from Linux 6 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include "armv7-m.dtsi" 48#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> 49 50/ { 51 clocks { 52 clk_hse: clk-hse { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <0>; 56 }; 57}; 58 59 soc { 60 u-boot,dm-pre-reloc; 61 mac: ethernet@40028000 { 62 compatible = "st,stm32-dwmac"; 63 reg = <0x40028000 0x8000>; 64 reg-names = "stmmaceth"; 65 interrupts = <61>, <62>; 66 interrupt-names = "macirq", "eth_wake_irq"; 67 snps,pbl = <8>; 68 snps,mixed-burst; 69 dma-ranges; 70 status = "disabled"; 71 }; 72 73 qspi: quadspi@A0001000 { 74 compatible = "st,stm32-qspi"; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; 78 reg-names = "QuadSPI", "QuadSPI-memory"; 79 interrupts = <92>; 80 spi-max-frequency = <108000000>; 81 clocks = <&rcc 0 65>; 82 status = "disabled"; 83 }; 84 usart1: serial@40011000 { 85 compatible = "st,stm32-usart", "st,stm32-uart"; 86 reg = <0x40011000 0x400>; 87 interrupts = <37>; 88 clocks = <&rcc 0 164>; 89 status = "disabled"; 90 u-boot,dm-pre-reloc; 91 }; 92 rcc: rcc@40023810 { 93 #reset-cells = <1>; 94 #clock-cells = <2>; 95 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 96 reg = <0x40023800 0x400>; 97 clocks = <&clk_hse>; 98 u-boot,dm-pre-reloc; 99 }; 100 101 pinctrl: pin-controller { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 compatible = "st,stm32f746-pinctrl"; 105 ranges = <0 0x40020000 0x3000>; 106 u-boot,dm-pre-reloc; 107 pins-are-numbered; 108 109 usart1_pins_a: usart1@0 { 110 pins1 { 111 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 112 bias-disable; 113 drive-push-pull; 114 slew-rate = <2>; 115 }; 116 pins2 { 117 pinmux = <STM32F746_PB7_FUNC_USART1_RX>; 118 bias-disable; 119 }; 120 }; 121 ethernet_mii: mii@0 { 122 pins { 123 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, 124 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, 125 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, 126 <STM32F746_PA2_FUNC_ETH_MDIO>, 127 <STM32F746_PC1_FUNC_ETH_MDC>, 128 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, 129 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, 130 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, 131 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; 132 slew-rate = <2>; 133 }; 134 }; 135 qspi_pins: qspi@0{ 136 pins { 137 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, 138 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, 139 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, 140 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, 141 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, 142 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; 143 slew-rate = <2>; 144 }; 145 }; 146 }; 147 }; 148}; 149 150&systick { 151 status = "okay"; 152}; 153