1/* 2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> 3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com> 4 * 5 * Based on: 6 * stm32f429.dtsi from Linux 7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of the 17 * License, or (at your option) any later version. 18 * 19 * This file is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "armv7-m.dtsi" 49#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> 50 51/ { 52 clocks { 53 clk_hse: clk-hse { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <0>; 57 }; 58}; 59 60 soc { 61 u-boot,dm-pre-reloc; 62 mac: ethernet@40028000 { 63 compatible = "st,stm32-dwmac"; 64 reg = <0x40028000 0x8000>; 65 reg-names = "stmmaceth"; 66 interrupts = <61>, <62>; 67 interrupt-names = "macirq", "eth_wake_irq"; 68 snps,pbl = <8>; 69 snps,mixed-burst; 70 dma-ranges; 71 status = "disabled"; 72 }; 73 74 fmc: fmc@A0000000 { 75 compatible = "st,stm32-fmc"; 76 reg = <0xA0000000 0x1000>; 77 u-boot,dm-pre-reloc; 78 }; 79 80 qspi: quadspi@A0001000 { 81 compatible = "st,stm32-qspi"; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; 85 reg-names = "QuadSPI", "QuadSPI-memory"; 86 interrupts = <92>; 87 spi-max-frequency = <108000000>; 88 clocks = <&rcc 0 65>; 89 status = "disabled"; 90 }; 91 usart1: serial@40011000 { 92 compatible = "st,stm32-usart", "st,stm32-uart"; 93 reg = <0x40011000 0x400>; 94 interrupts = <37>; 95 clocks = <&rcc 0 164>; 96 status = "disabled"; 97 u-boot,dm-pre-reloc; 98 }; 99 rcc: rcc@40023810 { 100 #reset-cells = <1>; 101 #clock-cells = <2>; 102 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 103 reg = <0x40023800 0x400>; 104 clocks = <&clk_hse>; 105 u-boot,dm-pre-reloc; 106 }; 107 108 pinctrl: pin-controller { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 compatible = "st,stm32f746-pinctrl"; 112 ranges = <0 0x40020000 0x3000>; 113 u-boot,dm-pre-reloc; 114 pins-are-numbered; 115 116 usart1_pins_a: usart1@0 { 117 pins1 { 118 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 119 bias-disable; 120 drive-push-pull; 121 slew-rate = <2>; 122 }; 123 pins2 { 124 pinmux = <STM32F746_PB7_FUNC_USART1_RX>; 125 bias-disable; 126 }; 127 }; 128 ethernet_mii: mii@0 { 129 pins { 130 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, 131 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, 132 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, 133 <STM32F746_PA2_FUNC_ETH_MDIO>, 134 <STM32F746_PC1_FUNC_ETH_MDC>, 135 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, 136 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, 137 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, 138 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; 139 slew-rate = <2>; 140 }; 141 }; 142 qspi_pins: qspi@0{ 143 pins { 144 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, 145 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, 146 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, 147 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, 148 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, 149 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; 150 slew-rate = <2>; 151 }; 152 }; 153 154 fmc_pins: fmc@0 { 155 pins { 156 pinmux = <STM32F746_PD10_FUNC_FMC_D15>, 157 <STM32F746_PD9_FUNC_FMC_D14>, 158 <STM32F746_PD8_FUNC_FMC_D13>, 159 <STM32F746_PE15_FUNC_FMC_D12>, 160 <STM32F746_PE14_FUNC_FMC_D11>, 161 <STM32F746_PE13_FUNC_FMC_D10>, 162 <STM32F746_PE12_FUNC_FMC_D9>, 163 <STM32F746_PE11_FUNC_FMC_D8>, 164 <STM32F746_PE10_FUNC_FMC_D7>, 165 <STM32F746_PE9_FUNC_FMC_D6>, 166 <STM32F746_PE8_FUNC_FMC_D5>, 167 <STM32F746_PE7_FUNC_FMC_D4>, 168 <STM32F746_PD1_FUNC_FMC_D3>, 169 <STM32F746_PD0_FUNC_FMC_D2>, 170 <STM32F746_PD15_FUNC_FMC_D1>, 171 <STM32F746_PD14_FUNC_FMC_D0>, 172 173 <STM32F746_PE1_FUNC_FMC_NBL1>, 174 <STM32F746_PE0_FUNC_FMC_NBL0>, 175 176 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, 177 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, 178 179 <STM32F746_PG1_FUNC_FMC_A11>, 180 <STM32F746_PG0_FUNC_FMC_A10>, 181 <STM32F746_PF15_FUNC_FMC_A9>, 182 <STM32F746_PF14_FUNC_FMC_A8>, 183 <STM32F746_PF13_FUNC_FMC_A7>, 184 <STM32F746_PF12_FUNC_FMC_A6>, 185 <STM32F746_PF5_FUNC_FMC_A5>, 186 <STM32F746_PF4_FUNC_FMC_A4>, 187 <STM32F746_PF3_FUNC_FMC_A3>, 188 <STM32F746_PF2_FUNC_FMC_A2>, 189 <STM32F746_PF1_FUNC_FMC_A1>, 190 <STM32F746_PF0_FUNC_FMC_A0>, 191 192 <STM32F746_PH3_FUNC_FMC_SDNE0>, 193 <STM32F746_PH5_FUNC_FMC_SDNWE>, 194 <STM32F746_PF11_FUNC_FMC_SDNRAS>, 195 <STM32F746_PG15_FUNC_FMC_SDNCAS>, 196 <STM32F746_PC3_FUNC_FMC_SDCKE0>, 197 <STM32F746_PG8_FUNC_FMC_SDCLK>; 198 slew-rate = <2>; 199 }; 200 }; 201 202 }; 203 }; 204}; 205 206&systick { 207 status = "okay"; 208}; 209