xref: /rk3399_rockchip-uboot/arch/arm/dts/stm32f746-disco.dts (revision 2f80a9f72ecf4cfee68279a45e3c155f6516faa1) 
1/*
2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
4 *
5 * Based on:
6 * stm32f469-disco.dts from Linux
7 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 *  a) This file is free software; you can redistribute it and/or
15 *     modify it under the terms of the GNU General Public License as
16 *     published by the Free Software Foundation; either version 2 of the
17 *     License, or (at your option) any later version.
18 *
19 *     This file is distributed in the hope that it will be useful,
20 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
21 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22 *     GNU General Public License for more details.
23 *
24 * Or, alternatively,
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use,
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "stm32f746.dtsi"
50#include <dt-bindings/memory/stm32-sdram.h>
51
52/ {
53	model = "STMicroelectronics STM32F746-DISCO board";
54	compatible = "st,stm32f746-disco", "st,stm32f746";
55
56	chosen {
57		bootargs = "root=/dev/ram rdinit=/linuxrc";
58		stdout-path = "serial0:115200n8";
59	};
60
61	memory {
62		reg = <0xC0000000 0x800000>;
63	};
64
65	aliases {
66		serial0 = &usart1;
67		spi0 = &qspi;
68		/* Aliases for gpios so as to use sequence */
69		gpio0 = &gpioa;
70		gpio1 = &gpiob;
71		gpio2 = &gpioc;
72		gpio3 = &gpiod;
73		gpio4 = &gpioe;
74		gpio5 = &gpiof;
75		gpio6 = &gpiog;
76		gpio7 = &gpioh;
77		gpio8 = &gpioi;
78		gpio9 = &gpioj;
79		gpio10 = &gpiok;
80	};
81
82	led1 {
83		compatible = "st,led1";
84		led-gpio = <&gpioi 1 0>;
85	};
86
87	button1 {
88		compatible = "st,button1";
89		button-gpio = <&gpioi 11 0>;
90	};
91};
92
93&clk_hse {
94	clock-frequency = <25000000>;
95};
96
97&usart1 {
98	pinctrl-0 = <&usart1_pins_a>;
99	pinctrl-names = "default";
100	status = "okay";
101};
102
103&fmc {
104	pinctrl-0 = <&fmc_pins>;
105	pinctrl-names = "default";
106	status = "okay";
107
108	mr-nbanks = <1>;
109	/* sdram memory configuration from sdram datasheet IS42S16400J */
110	bank1: bank@0 {
111	       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
112	       				    CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
113	       st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
114	       				   TRCD_18>;
115       };
116};
117
118&mac {
119	status = "okay";
120	pinctrl-0 = <&ethernet_mii>;
121	phy-mode = "rmii";
122	phy-handle = <&phy0>;
123
124	mdio0 {
125		#address-cells = <1>;
126		#size-cells = <0>;
127		compatible = "snps,dwmac-mdio";
128		phy0: ethernet-phy@0 {
129			reg = <0>;
130		};
131	};
132};
133
134&qspi {
135	pinctrl-0 = <&qspi_pins>;
136	status = "okay";
137
138	qflash0: n25q128a {
139			#address-cells = <1>;
140			#size-cells = <1>;
141			compatible = "micron,n25q128a13", "spi-flash";
142			spi-max-frequency = <108000000>;
143			spi-tx-bus-width = <1>;
144			spi-rx-bus-width = <1>;
145			memory-map = <0x90000000 0x1000000>;
146			reg = <0>;
147	};
148};
149