1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126b-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/phy/phy.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rockchip,rv1126b-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/soc/rockchip-system-status.h> 15 16/ { 17 compatible = "rockchip,rv1126b"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 aliases { 24 csi2dphy0 = &csi2_dphy0; 25 csi2dphy1 = &csi2_dphy1; 26 csi2dphy2 = &csi2_dphy2; 27 csi2dphy3 = &csi2_dphy3; 28 csi2dphy4 = &csi2_dphy4; 29 csi2dphy5 = &csi2_dphy5; 30 ethernet0 = &gmac; 31 gpio0 = &gpio0; 32 gpio1 = &gpio1; 33 gpio2 = &gpio2; 34 gpio3 = &gpio3; 35 gpio4 = &gpio4; 36 gpio5 = &gpio5; 37 gpio6 = &gpio6; 38 gpio7 = &gpio7; 39 i2c0 = &i2c0; 40 i2c1 = &i2c1; 41 i2c2 = &i2c2; 42 i2c3 = &i2c3; 43 i2c4 = &i2c4; 44 i2c5 = &i2c5; 45 mmc0 = &emmc; 46 mmc1 = &sdmmc0; 47 mmc2 = &sdmmc1; 48 rkcif_mipi_lvds0= &rkcif_mipi_lvds; 49 rkcif_mipi_lvds1= &rkcif_mipi_lvds1; 50 rkcif_mipi_lvds2= &rkcif_mipi_lvds2; 51 rkcif_mipi_lvds3= &rkcif_mipi_lvds3; 52 serial0 = &uart0; 53 serial1 = &uart1; 54 serial2 = &uart2; 55 serial3 = &uart3; 56 serial4 = &uart4; 57 serial5 = &uart5; 58 serial6 = &uart6; 59 serial7 = &uart7; 60 spi0 = &spi0; 61 spi1 = &spi1; 62 spi2 = &fspi0; 63 spi3 = &fspi1; 64 }; 65 66 clocks { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 mclkin_sai0: mclkin-sai0 { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <0>; 76 clock-output-names = "mclk_sai0_from_io"; 77 status = "disabled"; 78 }; 79 80 mclkin_sai1: mclkin-sai1 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <0>; 84 clock-output-names = "mclk_sai1_from_io"; 85 status = "disabled"; 86 }; 87 88 mclkin_sai2: mclkin-sai2 { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <0>; 92 clock-output-names = "mclk_sai2_from_io"; 93 status = "disabled"; 94 }; 95 96 sclkin_sai0: sclkin-sai0 { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <0>; 100 clock-output-names = "sclk_sai0_from_io"; 101 status = "disabled"; 102 }; 103 104 sclkin_sai1: sclkin-sai1 { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <0>; 108 clock-output-names = "sclk_sai1_from_io"; 109 status = "disabled"; 110 }; 111 112 sclkin_sai2: sclkin-sai2 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 clock-output-names = "sclk_sai2_from_io"; 117 status = "disabled"; 118 }; 119 120 xin32k: xin32k { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <32768>; 124 clock-output-names = "xin32k"; 125 }; 126 127 xin24m: xin24m { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <24000000>; 131 clock-output-names = "xin24m"; 132 }; 133 134 clk_rcosc: clk_rcosc { 135 compatible = "fixed-clock"; 136 #clock-cells = <0>; 137 clock-frequency = <96000000>; 138 clock-output-names = "clk_rcosc"; 139 }; 140 141 mclkout_sai0: mclkout-sai0@20100048 { 142 compatible = "rockchip,clk-out"; 143 reg = <0x20100048 0x4>; 144 clocks = <&cru MCLK_SAI0_OUT2IO>; 145 #clock-cells = <0>; 146 clock-output-names = "mclk_sai0_to_io"; 147 rockchip,bit-shift = <0>; 148 rockchip,bit-set-to-disable; 149 status = "disabled"; 150 }; 151 152 mclkout_sai1: mclkout-sai1@20100048 { 153 compatible = "rockchip,clk-out"; 154 reg = <0x20100048 0x4>; 155 clocks = <&cru MCLK_SAI1_OUT2IO>; 156 #clock-cells = <0>; 157 clock-output-names = "mclk_sai1_to_io"; 158 rockchip,bit-shift = <1>; 159 rockchip,bit-set-to-disable; 160 status = "disabled"; 161 }; 162 163 mclkout_sai2: mclkout-sai2@20100048 { 164 compatible = "rockchip,clk-out"; 165 reg = <0x20100048 0x4>; 166 clocks = <&cru MCLK_SAI2_OUT2IO>; 167 #clock-cells = <0>; 168 clock-output-names = "mclk_sai2_to_io"; 169 rockchip,bit-shift = <2>; 170 rockchip,bit-set-to-disable; 171 status = "disabled"; 172 }; 173 174 pvtpll_core: pvtpll-core@20480000 { 175 compatible = "rockchip,rv1126b-core-pvtpll", "syscon"; 176 reg = <0x20480000 0x100>; 177 clocks = <&cru ARMCLK>; 178 #clock-cells = <0>; 179 clock-output-names = "clk_core_pvtpll"; 180 assigned-clocks = <&pvtpll_core>; 181 assigned-clock-rates = <1200000000>; 182 }; 183 }; 184 185 cpus { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 189 cpu0: cpu@0 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a53"; 192 reg = <0x0>; 193 enable-method = "psci"; 194 clocks = <&cru ARMCLK>; 195 operating-points-v2 = <&cpu_opp_table>; 196 }; 197 cpu1: cpu@1 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a53"; 200 reg = <0x1>; 201 enable-method = "psci"; 202 clocks = <&cru ARMCLK>; 203 operating-points-v2 = <&cpu_opp_table>; 204 }; 205 cpu2: cpu@2 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-a53"; 208 reg = <0x2>; 209 enable-method = "psci"; 210 clocks = <&cru ARMCLK>; 211 operating-points-v2 = <&cpu_opp_table>; 212 }; 213 cpu3: cpu@3 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-a53"; 216 reg = <0x3>; 217 enable-method = "psci"; 218 clocks = <&cru ARMCLK>; 219 operating-points-v2 = <&cpu_opp_table>; 220 }; 221 }; 222 223 cpu_opp_table: cpu0-opp-table { 224 compatible = "operating-points-v2"; 225 opp-shared; 226 227 nvmem-cells = <&cpu_leakage>; 228 nvmem-cell-names = "leakage"; 229 230 opp-594000000 { 231 opp-hz = /bits/ 64 <594000000>; 232 opp-microvolt = <850000 850000 1100000>; 233 clock-latency-ns = <40000>; 234 opp-suspend; 235 }; 236 237 opp-816000000 { 238 opp-hz = /bits/ 64 <816000000>; 239 opp-microvolt = <850000 850000 1100000>; 240 clock-latency-ns = <40000>; 241 }; 242 opp-1008000000 { 243 opp-hz = /bits/ 64 <1008000000>; 244 opp-microvolt = <850000 850000 1100000>; 245 clock-latency-ns = <40000>; 246 }; 247 opp-1200000000 { 248 opp-hz = /bits/ 64 <1200000000>; 249 opp-microvolt = <862500 862500 1100000>; 250 clock-latency-ns = <40000>; 251 }; 252 opp-1296000000 { 253 opp-hz = /bits/ 64 <1296000000>; 254 opp-microvolt = <912500 912500 1100000>; 255 clock-latency-ns = <40000>; 256 }; 257 opp-1416000000 { 258 opp-hz = /bits/ 64 <1416000000>; 259 opp-microvolt = <937500 937500 1100000>; 260 clock-latency-ns = <40000>; 261 }; 262 opp-1512000000 { 263 opp-hz = /bits/ 64 <1512000000>; 264 opp-microvolt = <962500 962500 1100000>; 265 clock-latency-ns = <40000>; 266 }; 267 opp-1608000000 { 268 opp-hz = /bits/ 64 <1608000000>; 269 opp-microvolt = <1012500 1012500 1100000>; 270 clock-latency-ns = <40000>; 271 }; 272 }; 273 274 cpuinfo { 275 compatible = "rockchip,cpuinfo"; 276 nvmem-cells = <&otp_id>, <&cpu_version>, <&cpu_code>; 277 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 278 }; 279 280 /* dphy0 full mode */ 281 csi2_dphy0: csi2-dphy0 { 282 compatible = "rockchip,rv1126b-csi2-dphy"; 283 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 284 status = "disabled"; 285 }; 286 287 /* dphy0 split mode 01 */ 288 csi2_dphy1: csi2-dphy1 { 289 compatible = "rockchip,rv1126b-csi2-dphy"; 290 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 291 status = "disabled"; 292 }; 293 294 /* dphy0 split mode 23 */ 295 csi2_dphy2: csi2-dphy2 { 296 compatible = "rockchip,rv1126b-csi2-dphy"; 297 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 298 status = "disabled"; 299 }; 300 301 /* dphy1 full mode */ 302 csi2_dphy3: csi2-dphy3 { 303 compatible = "rockchip,rv1126b-csi2-dphy"; 304 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 305 status = "disabled"; 306 }; 307 308 /* dphy1 split mode 01 */ 309 csi2_dphy4: csi2-dphy4 { 310 compatible = "rockchip,rv1126b-csi2-dphy"; 311 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 312 status = "disabled"; 313 }; 314 315 /* dphy1 split mode 23 */ 316 csi2_dphy5: csi2-dphy5 { 317 compatible = "rockchip,rv1126b-csi2-dphy"; 318 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 319 status = "disabled"; 320 }; 321 322 display_subsystem: display-subsystem { 323 compatible = "rockchip,display-subsystem"; 324 ports = <&vop_out>; 325 status = "disabled"; 326 logo-memory-region = <&drm_logo>; 327 328 route { 329 route_dsi: route-dsi { 330 status = "disabled"; 331 logo,uboot = "logo.bmp"; 332 logo,kernel = "logo_kernel.bmp"; 333 logo,mode = "center"; 334 charge_logo,mode = "center"; 335 connect = <&vop_out_dsi>; 336 }; 337 338 route_rgb: route-rgb { 339 status = "disabled"; 340 logo,uboot = "logo.bmp"; 341 logo,kernel = "logo_kernel.bmp"; 342 logo,mode = "center"; 343 charge_logo,mode = "center"; 344 connect = <&vop_out_rgb>; 345 }; 346 }; 347 }; 348 349 fiq_debugger: fiq-debugger { 350 compatible = "rockchip,fiq-debugger"; 351 rockchip,serial-id = <0>; 352 rockchip,wake-irq = <0>; 353 rockchip,irq-mode-enable = <0>; 354 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 355 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 356 status = "disabled"; 357 }; 358 359 mipi0_csi2: mipi0-csi2 { 360 compatible = "rockchip,rv1126b-mipi-csi2"; 361 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 362 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 363 status = "disabled"; 364 }; 365 366 mipi1_csi2: mipi1-csi2 { 367 compatible = "rockchip,rv1126b-mipi-csi2"; 368 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 369 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 370 status = "disabled"; 371 }; 372 373 mipi2_csi2: mipi2-csi2 { 374 compatible = "rockchip,rv1126b-mipi-csi2"; 375 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 376 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 377 status = "disabled"; 378 }; 379 380 mipi3_csi2: mipi3-csi2 { 381 compatible = "rockchip,rv1126b-mipi-csi2"; 382 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 383 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 384 status = "disabled"; 385 }; 386 387 mpp_srv: mpp-srv { 388 compatible = "rockchip,mpp-service"; 389 rockchip,taskqueue-count = <3>; 390 rockchip,resetgroup-count = <3>; 391 status = "disabled"; 392 }; 393 394 mpp_vcodec: mpp-vcodec { 395 compatible = "rockchip,vcodec"; 396 status = "disabled"; 397 }; 398 399 pmu_a53: pmu-a53 { 400 compatible = "arm,cortex-a53-pmu"; 401 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 406 }; 407 408 psci: psci { 409 compatible = "arm,psci-1.0"; 410 method = "smc"; 411 }; 412 413 reserved-memory { 414 #address-cells = <1>; 415 #size-cells = <1>; 416 ranges; 417 418 drm_logo: drm-logo@0 { 419 compatible = "rockchip,drm-logo"; 420 reg = <0x0 0x0>; 421 }; 422 }; 423 424 rkaiisp_vir0: rkaiisp-vir0 { 425 compatible = "rockchip,rkaiisp-vir"; 426 rockchip,hw = <&rkaiisp>; 427 status = "disabled"; 428 }; 429 430 rkaiisp_vir1: rkaiisp-vir1 { 431 compatible = "rockchip,rkaiisp-vir"; 432 rockchip,hw = <&rkaiisp>; 433 status = "disabled"; 434 }; 435 436 rkaiisp_vir2: rkaiisp-vir2 { 437 compatible = "rockchip,rkaiisp-vir"; 438 rockchip,hw = <&rkaiisp>; 439 status = "disabled"; 440 }; 441 442 rkaiisp_vir3: rkaiisp-vir3 { 443 compatible = "rockchip,rkaiisp-vir"; 444 rockchip,hw = <&rkaiisp>; 445 status = "disabled"; 446 }; 447 448 rkcif_mipi_lvds: rkcif-mipi-lvds { 449 compatible = "rockchip,rkcif-mipi-lvds"; 450 rockchip,hw = <&rkcif>; 451 status = "disabled"; 452 }; 453 454 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 455 compatible = "rockchip,rkcif-sditf"; 456 rockchip,cif = <&rkcif_mipi_lvds>; 457 status = "disabled"; 458 }; 459 460 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { 461 compatible = "rockchip,rkcif-sditf"; 462 rockchip,cif = <&rkcif_mipi_lvds>; 463 status = "disabled"; 464 }; 465 466 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { 467 compatible = "rockchip,rkcif-sditf"; 468 rockchip,cif = <&rkcif_mipi_lvds>; 469 status = "disabled"; 470 }; 471 472 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { 473 compatible = "rockchip,rkcif-sditf"; 474 rockchip,cif = <&rkcif_mipi_lvds>; 475 status = "disabled"; 476 }; 477 478 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 479 compatible = "rockchip,rkcif-mipi-lvds"; 480 rockchip,hw = <&rkcif>; 481 status = "disabled"; 482 }; 483 484 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 485 compatible = "rockchip,rkcif-sditf"; 486 rockchip,cif = <&rkcif_mipi_lvds1>; 487 status = "disabled"; 488 }; 489 490 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { 491 compatible = "rockchip,rkcif-sditf"; 492 rockchip,cif = <&rkcif_mipi_lvds1>; 493 status = "disabled"; 494 }; 495 496 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { 497 compatible = "rockchip,rkcif-sditf"; 498 rockchip,cif = <&rkcif_mipi_lvds1>; 499 status = "disabled"; 500 }; 501 502 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { 503 compatible = "rockchip,rkcif-sditf"; 504 rockchip,cif = <&rkcif_mipi_lvds1>; 505 status = "disabled"; 506 }; 507 508 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 509 compatible = "rockchip,rkcif-mipi-lvds"; 510 rockchip,hw = <&rkcif>; 511 status = "disabled"; 512 }; 513 514 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 515 compatible = "rockchip,rkcif-sditf"; 516 rockchip,cif = <&rkcif_mipi_lvds2>; 517 status = "disabled"; 518 }; 519 520 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { 521 compatible = "rockchip,rkcif-sditf"; 522 rockchip,cif = <&rkcif_mipi_lvds2>; 523 status = "disabled"; 524 }; 525 526 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { 527 compatible = "rockchip,rkcif-sditf"; 528 rockchip,cif = <&rkcif_mipi_lvds2>; 529 status = "disabled"; 530 }; 531 532 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { 533 compatible = "rockchip,rkcif-sditf"; 534 rockchip,cif = <&rkcif_mipi_lvds2>; 535 status = "disabled"; 536 }; 537 538 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 539 compatible = "rockchip,rkcif-mipi-lvds"; 540 rockchip,hw = <&rkcif>; 541 status = "disabled"; 542 }; 543 544 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 545 compatible = "rockchip,rkcif-sditf"; 546 rockchip,cif = <&rkcif_mipi_lvds3>; 547 status = "disabled"; 548 }; 549 550 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { 551 compatible = "rockchip,rkcif-sditf"; 552 rockchip,cif = <&rkcif_mipi_lvds3>; 553 status = "disabled"; 554 }; 555 556 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { 557 compatible = "rockchip,rkcif-sditf"; 558 rockchip,cif = <&rkcif_mipi_lvds3>; 559 status = "disabled"; 560 }; 561 562 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { 563 compatible = "rockchip,rkcif-sditf"; 564 rockchip,cif = <&rkcif_mipi_lvds3>; 565 status = "disabled"; 566 }; 567 568 rkdvbm: rkdvbm { 569 compatible = "rockchip,rk-dvbm"; 570 status = "disabled"; 571 }; 572 573 rkisp_vir0: rkisp-vir0 { 574 compatible = "rockchip,rkisp-vir"; 575 rockchip,hw = <&rkisp>; 576 dvbm = <&rkdvbm>; 577 status = "disabled"; 578 }; 579 580 rkisp_vir1: rkisp-vir1 { 581 compatible = "rockchip,rkisp-vir"; 582 rockchip,hw = <&rkisp>; 583 dvbm = <&rkdvbm>; 584 status = "disabled"; 585 }; 586 587 rkisp_vir2: rkisp-vir2 { 588 compatible = "rockchip,rkisp-vir"; 589 rockchip,hw = <&rkisp>; 590 dvbm = <&rkdvbm>; 591 status = "disabled"; 592 }; 593 594 rkisp_vir3: rkisp-vir3 { 595 compatible = "rockchip,rkisp-vir"; 596 rockchip,hw = <&rkisp>; 597 dvbm = <&rkdvbm>; 598 status = "disabled"; 599 }; 600 601 rkisp_vir0_sditf: rkisp-vir0-sditf { 602 compatible = "rockchip,rkisp-sditf"; 603 rockchip,isp = <&rkisp_vir0>; 604 status = "disabled"; 605 606 port { 607 isp_sditf0: endpoint { 608 remote-endpoint = <&vpss0_in>; 609 }; 610 }; 611 }; 612 613 rkisp_vir1_sditf: rkisp-vir1-sditf { 614 compatible = "rockchip,rkisp-sditf"; 615 rockchip,isp = <&rkisp_vir1>; 616 status = "disabled"; 617 618 port { 619 isp_sditf1: endpoint { 620 remote-endpoint = <&vpss1_in>; 621 }; 622 }; 623 }; 624 625 rkisp_vir2_sditf: rkisp-vir2-sditf { 626 compatible = "rockchip,rkisp-sditf"; 627 rockchip,isp = <&rkisp_vir2>; 628 status = "disabled"; 629 630 port { 631 isp_sditf2: endpoint { 632 remote-endpoint = <&vpss2_in>; 633 }; 634 }; 635 }; 636 637 rkisp_vir3_sditf: rkisp-vir3-sditf { 638 compatible = "rockchip,rkisp-sditf"; 639 rockchip,isp = <&rkisp_vir3>; 640 status = "disabled"; 641 642 port { 643 isp_sditf3: endpoint { 644 remote-endpoint = <&vpss3_in>; 645 }; 646 }; 647 }; 648 649 rkvpss_vir0: rkvpss-vir0 { 650 compatible = "rockchip,rkvpss-vir"; 651 rockchip,hw = <&rkvpss>; 652 status = "disabled"; 653 654 port { 655 vpss0_in: endpoint { 656 remote-endpoint = <&isp_sditf0>; 657 }; 658 }; 659 }; 660 661 rkvpss_vir1: rkvpss-vir1 { 662 compatible = "rockchip,rkvpss-vir"; 663 rockchip,hw = <&rkvpss>; 664 status = "disabled"; 665 666 port { 667 vpss1_in: endpoint { 668 remote-endpoint = <&isp_sditf1>; 669 }; 670 }; 671 }; 672 673 rkvpss_vir2: rkvpss-vir2 { 674 compatible = "rockchip,rkvpss-vir"; 675 rockchip,hw = <&rkvpss>; 676 status = "disabled"; 677 678 port { 679 vpss2_in: endpoint { 680 remote-endpoint = <&isp_sditf2>; 681 }; 682 }; 683 }; 684 685 rkvpss_vir3: rkvpss-vir3 { 686 compatible = "rockchip,rkvpss-vir"; 687 rockchip,hw = <&rkvpss>; 688 status = "disabled"; 689 690 port { 691 vpss3_in: endpoint { 692 remote-endpoint = <&isp_sditf3>; 693 }; 694 }; 695 }; 696 697 rockchip_system_monitor: rockchip-system-monitor { 698 compatible = "rockchip,system-monitor"; 699 }; 700 701 thermal_zones: thermal-zones { 702 cpu_thermal: cpu-thermal { 703 polling-delay-passive = <20>; /* milliseconds */ 704 polling-delay = <1000>; /* milliseconds */ 705 thermal-sensors = <&tsadc 0>; 706 trips { 707 soc_crit: soc-crit { 708 /* millicelsius */ 709 temperature = <115000>; 710 /* millicelsius */ 711 hysteresis = <2000>; 712 type = "critical"; 713 }; 714 }; 715 }; 716 npu_thermal: npu-thermal { 717 polling-delay-passive = <20>; /* milliseconds */ 718 polling-delay = <1000>; /* milliseconds */ 719 thermal-sensors = <&tsadc 1>; 720 trips { 721 bigcore_crit: bigcore-crit { 722 /* millicelsius */ 723 temperature = <115000>; 724 /* millicelsius */ 725 hysteresis = <2000>; 726 type = "critical"; 727 }; 728 }; 729 }; 730 }; 731 732 timer { 733 compatible = "arm,armv8-timer"; 734 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 735 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 736 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 737 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 738 }; 739 740 cru: clock-controller@20000000 { 741 compatible = "rockchip,rv1126b-cru"; 742 reg = <0x20000000 0xc0000>; 743 #clock-cells = <1>; 744 #reset-cells = <1>; 745 746 assigned-clocks = 747 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 748 <&cru PLL_AUPLL>, <&cru CLK_AUDIO_FRAC0_SRC>, 749 <&cru CLK_AUDIO_FRAC1_SRC>, <&cru CLK_UART_FRAC0_SRC>, 750 <&cru CLK_UART_FRAC1_SRC>, <&cru CLK_CM_FRAC0_SRC>, 751 <&cru CLK_CM_FRAC1_SRC>, <&cru CLK_CM_FRAC2_SRC>, 752 <&cru CLK_UART_FRAC0>, <&cru CLK_UART_FRAC1>, 753 <&cru CLK_CM_FRAC0>, <&cru CLK_CM_FRAC1>, 754 <&cru CLK_CM_FRAC2>, <&cru CLK_AUDIO_FRAC0>, 755 <&cru CLK_AUDIO_FRAC1>; 756 assigned-clock-rates = 757 <1188000000>, <1000000000>, 758 <786432000>, <786432000>, 759 <786432000>, <1188000000>, 760 <1188000000>, <1188000000>, 761 <1188000000>, <786432000>, 762 <96000000>, <128000000>, 763 <18432000>, <500000000>, 764 <32768000>, <45158400>, 765 <49152000>; 766 }; 767 768 grf: syscon@20100000 { 769 compatible = "rockchip,rv1126b-grf", "syscon", "simple-mfd"; 770 reg = <0x20100000 0x91000>; 771 772 reboot_mode: reboot-mode { 773 compatible = "syscon-reboot-mode"; 774 offset = <0x30200>; 775 mode-bootloader = <BOOT_BL_DOWNLOAD>; 776 mode-charge = <BOOT_CHARGING>; 777 mode-fastboot = <BOOT_FASTBOOT>; 778 mode-loader = <BOOT_BL_DOWNLOAD>; 779 mode-normal = <BOOT_NORMAL>; 780 mode-recovery = <BOOT_RECOVERY>; 781 mode-ums = <BOOT_UMS>; 782 mode-panic = <BOOT_PANIC>; 783 mode-watchdog = <BOOT_WATCHDOG>; 784 }; 785 }; 786 787 ioc_grf: syscon@201a0000 { 788 compatible = "rockchip,rv1126b-ioc-grf", "syscon", "simple-mfd"; 789 reg = <0x201a0000 0x50000>; 790 791 rgb: rgb { 792 compatible = "rockchip,rv1126b-rgb"; 793 status = "disabled"; 794 795 ports { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 799 port@0 { 800 reg = <0>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 804 rgb_in_vop: endpoint@0 { 805 reg = <0>; 806 remote-endpoint = <&vop_out_rgb>; 807 }; 808 }; 809 810 }; 811 }; 812 }; 813 814 qos_cpu: qos@20310000 { 815 compatible = "syscon"; 816 reg = <0x20310000 0x20>; 817 }; 818 819 shaping_cpu: shaping@20310088 { 820 compatible = "syscon"; 821 reg = <0x20310088 0x4>; 822 }; 823 824 qos_emmc: qos@20320000 { 825 compatible = "syscon"; 826 reg = <0x20320000 0x20>; 827 }; 828 829 shaping_emmc: shaping@20320088 { 830 compatible = "syscon"; 831 reg = <0x20320088 0x4>; 832 }; 833 834 qos_fspi0: qos@20320100 { 835 compatible = "syscon"; 836 reg = <0x20320100 0x20>; 837 }; 838 839 shaping_fspi0: shaping@20320188 { 840 compatible = "syscon"; 841 reg = <0x20320188 0x4>; 842 }; 843 844 qos_usb2host: qos@20320200 { 845 compatible = "syscon"; 846 reg = <0x20320200 0x20>; 847 }; 848 849 shaping_usb2host: shaping@20320288 { 850 compatible = "syscon"; 851 reg = <0x20320288 0x4>; 852 }; 853 854 qos_usb3otg: qos@20320300 { 855 compatible = "syscon"; 856 reg = <0x20320300 0x20>; 857 }; 858 859 shaping_usb3otg: shaping@20320388 { 860 compatible = "syscon"; 861 reg = <0x20320388 0x4>; 862 }; 863 864 qos_gmac: qos@20330000 { 865 compatible = "syscon"; 866 reg = <0x20330000 0x20>; 867 }; 868 869 shaping_gmac: shaping@20330088 { 870 compatible = "syscon"; 871 reg = <0x20330088 0x4>; 872 }; 873 874 qos_isp: qos@20330100 { 875 compatible = "syscon"; 876 reg = <0x20330100 0x20>; 877 }; 878 879 shaping_isp: shaping@20330188 { 880 compatible = "syscon"; 881 reg = <0x20330188 0x4>; 882 }; 883 884 qos_rkcan0: qos@20330200 { 885 compatible = "syscon"; 886 reg = <0x20330200 0x20>; 887 }; 888 889 shaping_rkcan0: shaping@20330288 { 890 compatible = "syscon"; 891 reg = <0x20330288 0x4>; 892 }; 893 894 qos_rkcan1: qos@20330300 { 895 compatible = "syscon"; 896 reg = <0x20330300 0x20>; 897 }; 898 899 shaping_rkcan1: shaping@20330388 { 900 compatible = "syscon"; 901 reg = <0x20330388 0x4>; 902 }; 903 904 qos_sdmmc0: qos@20330400 { 905 compatible = "syscon"; 906 reg = <0x20330400 0x20>; 907 }; 908 909 shaping_sdmmc0: shaping@20330488 { 910 compatible = "syscon"; 911 reg = <0x20330488 0x4>; 912 }; 913 914 qos_vicap: qos@20330500 { 915 compatible = "syscon"; 916 reg = <0x20330500 0x20>; 917 }; 918 919 shaping_vicap: shaping@20330588 { 920 compatible = "syscon"; 921 reg = <0x20330588 0x4>; 922 }; 923 924 qos_vpsl: qos@20330600 { 925 compatible = "syscon"; 926 reg = <0x20330600 0x20>; 927 }; 928 929 shaping_vpsl: shaping@20330688 { 930 compatible = "syscon"; 931 reg = <0x20330688 0x4>; 932 }; 933 934 qos_vpss: qos@20330700 { 935 compatible = "syscon"; 936 reg = <0x20330700 0x20>; 937 }; 938 939 shaping_vpss: shaping@20330788 { 940 compatible = "syscon"; 941 reg = <0x20330788 0x4>; 942 }; 943 944 qos_saradc1: qos@20330800 { 945 compatible = "syscon"; 946 reg = <0x20330800 0x20>; 947 }; 948 949 shaping_saradc1: shaping@20330888 { 950 compatible = "syscon"; 951 reg = <0x20330888 0x4>; 952 }; 953 954 qos_saradc2: qos@20330900 { 955 compatible = "syscon"; 956 reg = <0x20330900 0x20>; 957 }; 958 959 shaping_saradc2: shaping@20330988 { 960 compatible = "syscon"; 961 reg = <0x20330988 0x4>; 962 }; 963 964 qos_npu: qos@20340000 { 965 compatible = "syscon"; 966 reg = <0x20340000 0x20>; 967 }; 968 969 shaping_npu: shaping@20340088 { 970 compatible = "syscon"; 971 reg = <0x20340088 0x4>; 972 }; 973 974 qos_rkvenc: qos@20350000 { 975 compatible = "syscon"; 976 reg = <0x20350000 0x20>; 977 }; 978 979 shaping_rkvenc: shaping@20350088 { 980 compatible = "syscon"; 981 reg = <0x20350088 0x4>; 982 }; 983 984 qos_saradc0: qos@20350100 { 985 compatible = "syscon"; 986 reg = <0x20350100 0x20>; 987 }; 988 989 shaping_saradc0: shaping@20350188 { 990 compatible = "syscon"; 991 reg = <0x20350188 0x4>; 992 }; 993 994 qos_sdmmc1: qos@20350200 { 995 compatible = "syscon"; 996 reg = <0x20350200 0x20>; 997 }; 998 999 shaping_sdmmc1: shaping@20350288 { 1000 compatible = "syscon"; 1001 reg = <0x20350288 0x4>; 1002 }; 1003 1004 qos_lpmcu: qos@20360000 { 1005 compatible = "syscon"; 1006 reg = <0x20360000 0x20>; 1007 }; 1008 1009 shaping_lpmcu: shaping@20360088 { 1010 compatible = "syscon"; 1011 reg = <0x20360088 0x4>; 1012 }; 1013 1014 qos_mcu: qos@20370100 { 1015 compatible = "syscon"; 1016 reg = <0x20370100 0x20>; 1017 }; 1018 1019 shaping_mcu: shaping@20370188 { 1020 compatible = "syscon"; 1021 reg = <0x20370188 0x4>; 1022 }; 1023 1024 qos_rga: qos@20370200 { 1025 compatible = "syscon"; 1026 reg = <0x20370200 0x20>; 1027 }; 1028 1029 shaping_rga: shaping@20370288 { 1030 compatible = "syscon"; 1031 reg = <0x20370288 0x4>; 1032 }; 1033 1034 qos_rkce: qos@20370400 { 1035 compatible = "syscon"; 1036 reg = <0x20370400 0x20>; 1037 }; 1038 1039 shaping_rkce: shaping@20370488 { 1040 compatible = "syscon"; 1041 reg = <0x20370488 0x4>; 1042 }; 1043 1044 qos_rkdma: qos@20370500 { 1045 compatible = "syscon"; 1046 reg = <0x20370500 0x20>; 1047 }; 1048 1049 shaping_rkdma: shaping@20370588 { 1050 compatible = "syscon"; 1051 reg = <0x20370588 0x4>; 1052 }; 1053 1054 qos_decom: qos@20380000 { 1055 compatible = "syscon"; 1056 reg = <0x20380000 0x20>; 1057 }; 1058 1059 shaping_decom: shaping@20380088 { 1060 compatible = "syscon"; 1061 reg = <0x20380088 0x4>; 1062 }; 1063 1064 qos_ooc: qos@20380100 { 1065 compatible = "syscon"; 1066 reg = <0x20380100 0x20>; 1067 }; 1068 1069 shaping_ooc: shaping@20380188 { 1070 compatible = "syscon"; 1071 reg = <0x20380188 0x4>; 1072 }; 1073 1074 qos_rkjpeg: qos@20380200 { 1075 compatible = "syscon"; 1076 reg = <0x20380200 0x20>; 1077 }; 1078 1079 shaping_rkjpeg: shaping@20380288 { 1080 compatible = "syscon"; 1081 reg = <0x20380288 0x4>; 1082 }; 1083 1084 qos_rkvdec: qos@20380300 { 1085 compatible = "syscon"; 1086 reg = <0x20380300 0x20>; 1087 }; 1088 1089 shaping_rkvdec: shaping@20380388 { 1090 compatible = "syscon"; 1091 reg = <0x20380388 0x4>; 1092 }; 1093 1094 qos_vop: qos@20380400 { 1095 compatible = "syscon"; 1096 reg = <0x20380400 0x20>; 1097 }; 1098 1099 shaping_vop: shaping@20380488 { 1100 compatible = "syscon"; 1101 reg = <0x20380488 0x4>; 1102 }; 1103 1104 qos_avsp_ro: qos@20390000 { 1105 compatible = "syscon"; 1106 reg = <0x20390000 0x20>; 1107 }; 1108 1109 shaping_avsp_ro: shaping@20390088 { 1110 compatible = "syscon"; 1111 reg = <0x20390088 0x4>; 1112 }; 1113 1114 qos_avsp_wo: qos@20390100 { 1115 compatible = "syscon"; 1116 reg = <0x20390100 0x20>; 1117 }; 1118 1119 shaping_avsp_wo: shaping@20390188 { 1120 compatible = "syscon"; 1121 reg = <0x20390188 0x4>; 1122 }; 1123 1124 qos_fec_ro: qos@20390200 { 1125 compatible = "syscon"; 1126 reg = <0x20390200 0x20>; 1127 }; 1128 1129 shaping_fec_ro: shaping@20390288 { 1130 compatible = "syscon"; 1131 reg = <0x20390288 0x4>; 1132 }; 1133 1134 qos_fec_wo: qos@20390300 { 1135 compatible = "syscon"; 1136 reg = <0x20390300 0x20>; 1137 }; 1138 1139 shaping_fec_wo: shaping@20390388 { 1140 compatible = "syscon"; 1141 reg = <0x20390388 0x4>; 1142 }; 1143 1144 qos_aad: qos@203a0000 { 1145 compatible = "syscon"; 1146 reg = <0x203a0000 0x20>; 1147 }; 1148 1149 shaping_aad: shaping@203a0088 { 1150 compatible = "syscon"; 1151 reg = <0x203a0088 0x4>; 1152 }; 1153 1154 qos_afe: qos@203a0100 { 1155 compatible = "syscon"; 1156 reg = <0x203a0100 0x20>; 1157 }; 1158 1159 shaping_afe: shaping@203a0188 { 1160 compatible = "syscon"; 1161 reg = <0x203a0188 0x4>; 1162 }; 1163 1164 qos_atdd: qos@203a0200 { 1165 compatible = "syscon"; 1166 reg = <0x203a0200 0x20>; 1167 }; 1168 1169 shaping_atdd: shaping@203a0288 { 1170 compatible = "syscon"; 1171 reg = <0x203a0288 0x4>; 1172 }; 1173 1174 qos_fspi1: qos@203a0300 { 1175 compatible = "syscon"; 1176 reg = <0x203a0300 0x20>; 1177 }; 1178 1179 shaping_fspi1: shaping@203a0388 { 1180 compatible = "syscon"; 1181 reg = <0x203a0388 0x4>; 1182 }; 1183 1184 qos_lpdma: qos@203a0400 { 1185 compatible = "syscon"; 1186 reg = <0x203a0400 0x20>; 1187 }; 1188 1189 shaping_lpdma: shaping@203a0488 { 1190 compatible = "syscon"; 1191 reg = <0x203a0488 0x4>; 1192 }; 1193 1194 qos_spi2ahb: qos@203a0500 { 1195 compatible = "syscon"; 1196 reg = <0x203a0500 0x20>; 1197 }; 1198 1199 shaping_spi2ahb: shaping@203a0588 { 1200 compatible = "syscon"; 1201 reg = <0x203a0588 0x4>; 1202 }; 1203 1204 qos_aisp: qos@203b0000 { 1205 compatible = "syscon"; 1206 reg = <0x203b0000 0x20>; 1207 }; 1208 1209 lpmcu_mbox0: mailbox@20500000 { 1210 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1211 reg = <0x20500000 0x20>; 1212 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&cru PCLK_LPMCU_MAILBOX>; 1214 clock-names = "pclk_mailbox"; 1215 #mbox-cells = <1>; 1216 status = "disabled"; 1217 }; 1218 1219 lpmcu_mbox1: mailbox@20510000 { 1220 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1221 reg = <0x20510000 0x20>; 1222 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&cru PCLK_LPMCU_MAILBOX>; 1224 clock-names = "pclk_mailbox"; 1225 #mbox-cells = <1>; 1226 status = "disabled"; 1227 }; 1228 1229 lpmcu_mbox2: mailbox@20520000 { 1230 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1231 reg = <0x20520000 0x20>; 1232 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&cru PCLK_LPMCU_MAILBOX>; 1234 clock-names = "pclk_mailbox"; 1235 #mbox-cells = <1>; 1236 status = "disabled"; 1237 }; 1238 1239 lpmcu_mbox3: mailbox@20530000 { 1240 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1241 reg = <0x20530000 0x20>; 1242 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&cru PCLK_LPMCU_MAILBOX>; 1244 clock-names = "pclk_mailbox"; 1245 #mbox-cells = <1>; 1246 status = "disabled"; 1247 }; 1248 1249 pwm1_4ch_0: pwm@20700000 { 1250 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1251 reg = <0x20700000 0x1000>; 1252 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1254 clock-names = "pwm", "pclk"; 1255 pinctrl-names = "active"; 1256 pinctrl-0 = <&pwm1m0_ch0_pins>; 1257 #pwm-cells = <3>; 1258 status = "disabled"; 1259 }; 1260 1261 pwm1_4ch_1: pwm@20710000 { 1262 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1263 reg = <0x20710000 0x1000>; 1264 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1266 clock-names = "pwm", "pclk"; 1267 pinctrl-names = "active"; 1268 pinctrl-0 = <&pwm1m0_ch1_pins>; 1269 #pwm-cells = <3>; 1270 status = "disabled"; 1271 }; 1272 1273 pwm1_4ch_2: pwm@20720000 { 1274 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1275 reg = <0x20720000 0x1000>; 1276 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1278 clock-names = "pwm", "pclk"; 1279 pinctrl-names = "active"; 1280 pinctrl-0 = <&pwm1m0_ch2_pins>; 1281 #pwm-cells = <3>; 1282 status = "disabled"; 1283 }; 1284 1285 pwm1_4ch_3: pwm@20730000 { 1286 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1287 reg = <0x20730000 0x1000>; 1288 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1290 clock-names = "pwm", "pclk"; 1291 pinctrl-names = "active"; 1292 pinctrl-0 = <&pwm1m0_ch3_pins>; 1293 #pwm-cells = <3>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c2: i2c@20800000 { 1298 compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; 1299 reg = <0x20800000 0x1000>; 1300 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1304 clock-names = "i2c", "pclk"; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&i2c2m0_pins>; 1307 status = "disabled"; 1308 }; 1309 1310 uart0: serial@20810000 { 1311 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 1312 reg = <0x20810000 0x100>; 1313 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1315 clock-names = "baudclk", "apb_pclk"; 1316 reg-shift = <2>; 1317 reg-io-width = <4>; 1318 dmas = <&dmac 1>, <&dmac 0>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&uart0m0_xfer_pins>; 1321 status = "disabled"; 1322 }; 1323 1324 pmu: power-management@20838000 { 1325 compatible = "rockchip,rv1126b-pmu", "syscon", "simple-mfd"; 1326 reg = <0x20838000 0x400>; 1327 1328 power: power-controller { 1329 compatible = "rockchip,rv1126b-power-controller"; 1330 #power-domain-cells = <1>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "okay"; 1334 1335 /* These power domains are grouped by VD_NPU */ 1336 power-domain@RV1126B_PD_NPU { 1337 reg = <RV1126B_PD_NPU>; 1338 pm_qos = <&qos_npu>; 1339 pm_shaping = <&shaping_npu>; 1340 }; 1341 /* These power domains are grouped by VD_LOGIC */ 1342 power-domain@RV1126B_PD_VDO { 1343 reg = <RV1126B_PD_VDO>; 1344 pm_qos = <&qos_vop>, 1345 <&qos_rkvdec>, 1346 <&qos_rkjpeg>, 1347 <&qos_decom>; 1348 pm_shaping = <&shaping_vop>, 1349 <&shaping_rkvdec>, 1350 <&shaping_rkjpeg>, 1351 <&shaping_decom>; 1352 }; 1353 power-domain@RV1126B_PD_AISP { 1354 reg = <RV1126B_PD_AISP>; 1355 pm_qos = <&qos_aisp>; 1356 }; 1357 }; 1358 }; 1359 1360 audio_codec_pmu: audio-codec@20890000 { 1361 compatible = "rockchip,rv1126b-codec", "rockchip,rk3506-codec"; 1362 reg = <0x20890000 0x1000>; 1363 #sound-dai-cells = <0>; 1364 sound-name-prefix = "ACodec_LP"; 1365 clocks = <&cru PCLK_AUDIO_ADC_PMU>, <&cru MCLK_AUDIO_ADC_PMU>; 1366 clock-names = "pclk", "mclk"; 1367 resets = <&cru SRST_MRESETN_AUDIO_ADC_PMU>; 1368 reset-names = "rst"; 1369 rockchip,grf = <&grf>; 1370 status = "disabled"; 1371 }; 1372 1373 fspi1: spi@208c0000 { 1374 compatible = "rockchip,rv1126b-fspi", "rockchip,fspi"; 1375 reg = <0x208c0000 0x4000>; 1376 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&cru SCLK_1X_FSPI1>, <&cru HCLK_FSPI1>; 1378 clock-names = "clk_sfc", "hclk_sfc"; 1379 rockchip,grf = <&grf>; 1380 rockchip,max-dll = <0x7F>; 1381 rockchip,sclk-x2-bypass; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 crypto: crypto@20940000 { 1388 compatible = "rockchip,crypto-ce"; 1389 reg = <0x20940000 0x2000>; 1390 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&cru ACLK_NSRKCE>, <&cru HCLK_NS_RKCE>, 1392 <&cru CLK_PKA_NSRKCE>; 1393 clock-names = "aclk", "hclk", "pka"; 1394 resets = <&cru SRST_HRESETN_NS_RKCE>; 1395 reset-names = "crypto-rst"; 1396 status = "disabled"; 1397 }; 1398 1399 rng: rng@20950000 { 1400 compatible = "rockchip,rkrng"; 1401 reg = <0x20950000 0x200>; 1402 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1403 resets = <&cru SRST_HRESETN_RKRNG_NS>; 1404 reset-names = "reset"; 1405 status = "disabled"; 1406 }; 1407 1408 sai0: sai@20960000 { 1409 compatible = "rockchip,rv1126b-sai", "rockchip,sai-v1"; 1410 reg = <0x20960000 0x1000>; 1411 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; 1413 clock-names = "mclk", "hclk"; 1414 dmas = <&dmac 17>, <&dmac 16>; 1415 dma-names = "tx", "rx"; 1416 resets = <&cru SRST_MRESETN_SAI0>, <&cru SRST_HRESETN_SAI0>; 1417 reset-names = "m", "h"; 1418 #sound-dai-cells = <0>; 1419 sound-name-prefix = "SAI0"; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&sai0m0_lrck_pins 1422 &sai0m0_sclk_pins 1423 &sai0m0_sdi0_pins 1424 &sai0m0_sdi1_pins 1425 &sai0m0_sdi2_pins 1426 &sai0m0_sdi3_pins 1427 &sai0m0_sdo0_pins>; 1428 status = "disabled"; 1429 }; 1430 1431 sai1: sai@20970000 { 1432 compatible = "rockchip,rv1126b-sai", "rockchip,sai-v1"; 1433 reg = <0x20970000 0x1000>; 1434 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; 1436 clock-names = "mclk", "hclk"; 1437 dmas = <&dmac 19>, <&dmac 18>; 1438 dma-names = "tx", "rx"; 1439 resets = <&cru SRST_MRESETN_SAI1>, <&cru SRST_HRESETN_SAI1>; 1440 reset-names = "m", "h"; 1441 #sound-dai-cells = <0>; 1442 sound-name-prefix = "SAI1"; 1443 pinctrl-names = "default"; 1444 pinctrl-0 = <&sai1m0_lrck_pins 1445 &sai1m0_sclk_pins 1446 &sai1m0_sdi_pins 1447 &sai1m0_sdo_pins>; 1448 status = "disabled"; 1449 }; 1450 1451 sai2: sai@20980000 { 1452 compatible = "rockchip,rv1126b-sai", "rockchip,sai-v1"; 1453 reg = <0x20980000 0x1000>; 1454 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; 1456 clock-names = "mclk", "hclk"; 1457 dmas = <&dmac 21>, <&dmac 20>; 1458 dma-names = "tx", "rx"; 1459 resets = <&cru SRST_MRESETN_SAI2>, <&cru SRST_HRESETN_SAI2>; 1460 reset-names = "m", "h"; 1461 #sound-dai-cells = <0>; 1462 sound-name-prefix = "SAI2"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&sai2m0_lrck_pins 1465 &sai2m0_sclk_pins 1466 &sai2m0_sdi0_pins 1467 &sai2m0_sdi1_pins 1468 &sai2m0_sdi2_pins 1469 &sai2m0_sdo_pins>; 1470 status = "disabled"; 1471 }; 1472 1473 pdm: pdm@20990000 { 1474 compatible = "rockchip,rv1126b-pdm", "rockchip,rk3576-pdm"; 1475 reg = <0x20990000 0x1000>; 1476 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>; 1478 clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; 1479 dmas = <&dmac 26>; 1480 dma-names = "rx"; 1481 rockchip,pdm-data-shift = <5 5 5 5 5 5 5 5>; 1482 pinctrl-names = "default", "idle", "clk"; 1483 pinctrl-0 = <&pdmm0_sdi0_pins 1484 &pdmm0_sdi1_pins 1485 &pdmm0_sdi2_pins 1486 &pdmm0_sdi3_pins>; 1487 pinctrl-1 = <&pdmm0_clk0_idle 1488 &pdmm0_clk1_idle>; 1489 pinctrl-2 = <&pdmm0_clk0_pins 1490 &pdmm0_clk1_pins>; 1491 #sound-dai-cells = <0>; 1492 sound-name-prefix = "PDM0"; 1493 status = "disabled"; 1494 }; 1495 1496 acdcdig_dsm: acdcdig-dsm@209a0000 { 1497 compatible = "rockchip,rv1126b-dsm"; 1498 reg = <0x209a0000 0x1000>; 1499 clocks = <&cru MCLK_RKDSM>, <&cru HCLK_RKDSM>; 1500 clock-names = "dac", "pclk"; 1501 resets = <&cru SRST_MRESETN_RKDSM>; 1502 reset-names = "reset" ; 1503 rockchip,grf = <&grf>; 1504 rockchip,ioc-grf = <&ioc_grf>; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&dsm_aud_ln_pins 1507 &dsm_aud_lp_pins 1508 &dsm_aud_rn_pins 1509 &dsm_aud_rp_pins>; 1510 #sound-dai-cells = <0>; 1511 status = "disabled"; 1512 }; 1513 1514 asrc0: asrc@209b0000 { 1515 compatible = "rockchip,rv1126b-asrc", "rockchip,rk3506-asrc"; 1516 reg = <0x209b0000 0x1000>; 1517 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&cru CLK_ASRC0>, <&cru HCLK_ASRC0>, 1519 <&cru LRCK_SRC_ASRC0>, <&cru LRCK_DST_ASRC0>; 1520 clock-names = "mclk", "hclk", 1521 "src_lrck", "dst_lrck"; 1522 dmas = <&dmac 22>, <&dmac 23>; 1523 dma-names = "rx", "tx"; 1524 resets = <&cru SRST_RESETN_ASRC0>, <&cru SRST_HRESETN_ASRC0>; 1525 reset-names = "m", "h"; 1526 #sound-dai-cells = <0>; 1527 sound-name-prefix = "ASRC0"; 1528 status = "disabled"; 1529 }; 1530 1531 asrc1: asrc@209c0000 { 1532 compatible = "rockchip,rv1126b-asrc", "rockchip,rk3506-asrc"; 1533 reg = <0x209c0000 0x1000>; 1534 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1535 clocks = <&cru CLK_ASRC1>, <&cru HCLK_ASRC1>, 1536 <&cru LRCK_SRC_ASRC1>, <&cru LRCK_DST_ASRC1>; 1537 clock-names = "mclk", "hclk", 1538 "src_lrck", "dst_lrck"; 1539 dmas = <&dmac 24>, <&dmac 25>; 1540 dma-names = "rx", "tx"; 1541 resets = <&cru SRST_RESETN_ASRC1>, <&cru SRST_HRESETN_ASRC1>; 1542 reset-names = "m", "h"; 1543 #sound-dai-cells = <0>; 1544 sound-name-prefix = "ASRC1"; 1545 status = "disabled"; 1546 }; 1547 1548 rga2_core0: rga@209f0000 { 1549 compatible = "rockchip,rga2"; 1550 reg = <0x209f0000 0x1000>; 1551 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1552 interrupt-names = "rga2_core0_irq"; 1553 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; 1554 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1555 iommus = <&rga2_core0_mmu>; 1556 status = "disabled"; 1557 }; 1558 1559 rga2_core0_mmu: iommu@209f0f00 { 1560 compatible = "rockchip,iommu-v2"; 1561 reg = <0x209f0f00 0x100>; 1562 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1563 interrupt-names = "rga2_0_mmu"; 1564 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1565 clock-names = "aclk", "iface"; 1566 #iommu-cells = <0>; 1567 status = "disabled"; 1568 }; 1569 1570 wdt: watchdog@20b60000 { 1571 compatible = "snps,dw-wdt"; 1572 reg = <0x20b60000 0x100>; 1573 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1574 clock-names = "tclk", "pclk"; 1575 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1576 status = "disabled"; 1577 }; 1578 1579 dmac: dma-controller@20b80000 { 1580 compatible = "rockchip,rv1126b-dma", "rockchip,dma"; 1581 reg = <0x20b80000 0x2000>; 1582 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&cru ACLK_RKDMA>; 1584 clock-names = "aclk"; 1585 #dma-cells = <1>; 1586 }; 1587 1588 otp: otp@20b90000 { 1589 compatible = "rockchip,rv1126b-otp"; 1590 reg = <0x20b90000 0x4000>; 1591 #address-cells = <1>; 1592 #size-cells = <1>; 1593 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 1594 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>; 1595 clock-names = "usr", "sbpi", "apb", "phy"; 1596 resets = <&cru SRST_RESETN_USER_OTPC_NS>, <&cru SRST_RESETN_SBPI_OTPC_NS>, 1597 <&cru SRST_PRESETN_OTPC_NS>, <&cru SRST_PRESETN_OTP_MASK>; 1598 reset-names = "usr", "sbpi", "apb", "phy"; 1599 1600 /* Data cells */ 1601 cpu_code: cpu-code@2 { 1602 reg = <0x02 0x2>; 1603 }; 1604 cpu_version: cpu-version@21 { 1605 reg = <0x21 0x1>; 1606 bits = <3 3>; 1607 }; 1608 otp_id: otp-id@22 { 1609 reg = <0x22 0x10>; 1610 }; 1611 cpu_leakage: cpu-leakage@32 { 1612 reg = <0x32 0x1>; 1613 }; 1614 log_leakage: log-leakage@33 { 1615 reg = <0x33 0x1>; 1616 }; 1617 npu_leakage: npu-leakage@34 { 1618 reg = <0x34 0x1>; 1619 }; 1620 }; 1621 1622 tsadc: tsadc@20bb0000 { 1623 compatible = "rockchip,rv1126b-tsadc"; 1624 reg = <0x20bb0000 0x400>; 1625 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, 1627 <&cru CLK_TSADC_PHYCTRL>; 1628 clock-names = "tsadc", "apb_pclk", "tsadc_phyctrl"; 1629 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>, 1630 <&cru SRST_RESETN_TSADC_PHYCTRL>; 1631 reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 1632 #thermal-sensor-cells = <1>; 1633 rockchip,grf = <&grf>; 1634 rockchip,hw-tshut-temp = <120000>; 1635 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1636 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1637 status = "disabled"; 1638 }; 1639 1640 audio_codec: audio-codec@20bf0000 { 1641 compatible = "rockchip,rv1126b-codec", "rockchip,rk3506-codec"; 1642 reg = <0x20bf0000 0x1000>; 1643 #sound-dai-cells = <0>; 1644 sound-name-prefix = "ACodec"; 1645 clocks = <&cru PCLK_AUDIO_ADC_BUS>, <&cru MCLK_AUDIO_ADC_BUS>; 1646 clock-names = "pclk", "mclk"; 1647 resets = <&cru SRST_MRESETN_AUDIO_ADC_BUS>; 1648 reset-names = "rst"; 1649 rockchip,grf = <&grf>; 1650 status = "disabled"; 1651 }; 1652 1653 rktimer: timer@20c00000 { 1654 compatible = "rockchip,rv1126b-timer", "rockchip,rk3288-timer"; 1655 reg = <0x20c00000 0x20>; 1656 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 1658 clock-names = "pclk", "timer"; 1659 }; 1660 1661 hpmcu_mbox0: mailbox@20d00000 { 1662 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1663 reg = <0x20d00000 0x20>; 1664 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&cru PCLK_HPMCU_MAILBOX>; 1666 clock-names = "pclk_mailbox"; 1667 #mbox-cells = <1>; 1668 status = "disabled"; 1669 }; 1670 1671 hpmcu_mbox1: mailbox@20d10000 { 1672 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1673 reg = <0x20d10000 0x20>; 1674 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1675 clocks = <&cru PCLK_HPMCU_MAILBOX>; 1676 clock-names = "pclk_mailbox"; 1677 #mbox-cells = <1>; 1678 status = "disabled"; 1679 }; 1680 1681 hpmcu_mbox2: mailbox@20d20000 { 1682 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1683 reg = <0x20d20000 0x20>; 1684 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1685 clocks = <&cru PCLK_HPMCU_MAILBOX>; 1686 clock-names = "pclk_mailbox"; 1687 #mbox-cells = <1>; 1688 status = "disabled"; 1689 }; 1690 1691 hpmcu_mbox3: mailbox@20d30000 { 1692 compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; 1693 reg = <0x20d30000 0x20>; 1694 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1695 clocks = <&cru PCLK_HPMCU_MAILBOX>; 1696 clock-names = "pclk_mailbox"; 1697 #mbox-cells = <1>; 1698 status = "disabled"; 1699 }; 1700 1701 pwm0_8ch_0: pwm@20e00000 { 1702 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1703 reg = <0x20e00000 0x1000>; 1704 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1705 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1706 clock-names = "pwm", "pclk"; 1707 pinctrl-names = "active"; 1708 pinctrl-0 = <&pwm0m0_ch0_pins>; 1709 #pwm-cells = <3>; 1710 status = "disabled"; 1711 }; 1712 1713 pwm0_8ch_1: pwm@20e10000 { 1714 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1715 reg = <0x20e10000 0x1000>; 1716 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1717 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1718 clock-names = "pwm", "pclk"; 1719 pinctrl-names = "active"; 1720 pinctrl-0 = <&pwm0m0_ch1_pins>; 1721 #pwm-cells = <3>; 1722 status = "disabled"; 1723 }; 1724 1725 pwm0_8ch_2: pwm@20e20000 { 1726 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1727 reg = <0x20e20000 0x1000>; 1728 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1729 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1730 clock-names = "pwm", "pclk"; 1731 pinctrl-names = "active"; 1732 pinctrl-0 = <&pwm0m0_ch2_pins>; 1733 #pwm-cells = <3>; 1734 status = "disabled"; 1735 }; 1736 1737 pwm0_8ch_3: pwm@20e30000 { 1738 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1739 reg = <0x20e30000 0x1000>; 1740 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1741 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1742 clock-names = "pwm", "pclk"; 1743 pinctrl-names = "active"; 1744 pinctrl-0 = <&pwm0m0_ch3_pins>; 1745 #pwm-cells = <3>; 1746 status = "disabled"; 1747 }; 1748 1749 pwm0_8ch_4: pwm@20e40000 { 1750 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1751 reg = <0x20e40000 0x1000>; 1752 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1753 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1754 clock-names = "pwm", "pclk"; 1755 pinctrl-names = "active"; 1756 pinctrl-0 = <&pwm0m0_ch4_pins>; 1757 #pwm-cells = <3>; 1758 status = "disabled"; 1759 }; 1760 1761 pwm0_8ch_5: pwm@20e50000 { 1762 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1763 reg = <0x20e50000 0x1000>; 1764 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1765 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1766 clock-names = "pwm", "pclk"; 1767 pinctrl-names = "active"; 1768 pinctrl-0 = <&pwm0m0_ch5_pins>; 1769 #pwm-cells = <3>; 1770 status = "disabled"; 1771 }; 1772 1773 pwm0_8ch_6: pwm@20e60000 { 1774 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1775 reg = <0x20e60000 0x1000>; 1776 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1777 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1778 clock-names = "pwm", "pclk"; 1779 pinctrl-names = "active"; 1780 pinctrl-0 = <&pwm0m0_ch6_pins>; 1781 #pwm-cells = <3>; 1782 status = "disabled"; 1783 }; 1784 1785 pwm0_8ch_7: pwm@20e70000 { 1786 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1787 reg = <0x20e70000 0x1000>; 1788 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1789 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1790 clock-names = "pwm", "pclk"; 1791 pinctrl-names = "active"; 1792 pinctrl-0 = <&pwm0m0_ch7_pins>; 1793 #pwm-cells = <3>; 1794 status = "disabled"; 1795 }; 1796 1797 pwm2_8ch_0: pwm@20f00000 { 1798 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1799 reg = <0x20f00000 0x1000>; 1800 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1802 clock-names = "pwm", "pclk", "osc"; 1803 pinctrl-names = "active"; 1804 pinctrl-0 = <&pwm2m0_ch0_pins>; 1805 #pwm-cells = <3>; 1806 status = "disabled"; 1807 }; 1808 1809 pwm2_8ch_1: pwm@20f10000 { 1810 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1811 reg = <0x20f10000 0x1000>; 1812 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1813 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1814 clock-names = "pwm", "pclk", "osc"; 1815 pinctrl-names = "active"; 1816 pinctrl-0 = <&pwm2m0_ch1_pins>; 1817 #pwm-cells = <3>; 1818 status = "disabled"; 1819 }; 1820 1821 pwm2_8ch_2: pwm@20f20000 { 1822 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1823 reg = <0x20f20000 0x1000>; 1824 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1825 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1826 clock-names = "pwm", "pclk", "osc"; 1827 pinctrl-names = "active"; 1828 pinctrl-0 = <&pwm2m0_ch2_pins>; 1829 #pwm-cells = <3>; 1830 status = "disabled"; 1831 }; 1832 1833 pwm2_8ch_3: pwm@20f30000 { 1834 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1835 reg = <0x20f30000 0x1000>; 1836 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1837 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1838 clock-names = "pwm", "pclk", "osc"; 1839 pinctrl-names = "active"; 1840 pinctrl-0 = <&pwm2m0_ch3_pins>; 1841 #pwm-cells = <3>; 1842 status = "disabled"; 1843 }; 1844 1845 pwm2_8ch_4: pwm@20f40000 { 1846 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1847 reg = <0x20f40000 0x1000>; 1848 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1849 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1850 clock-names = "pwm", "pclk", "osc"; 1851 pinctrl-names = "active"; 1852 pinctrl-0 = <&pwm2m0_ch4_pins>; 1853 #pwm-cells = <3>; 1854 status = "disabled"; 1855 }; 1856 1857 pwm2_8ch_5: pwm@20f50000 { 1858 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1859 reg = <0x20f50000 0x1000>; 1860 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1861 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1862 clock-names = "pwm", "pclk", "osc"; 1863 pinctrl-names = "active"; 1864 pinctrl-0 = <&pwm2m0_ch5_pins>; 1865 #pwm-cells = <3>; 1866 status = "disabled"; 1867 }; 1868 1869 pwm2_8ch_6: pwm@20f60000 { 1870 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1871 reg = <0x20f60000 0x1000>; 1872 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1873 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1874 clock-names = "pwm", "pclk", "osc"; 1875 pinctrl-names = "active"; 1876 pinctrl-0 = <&pwm2m0_ch6_pins>; 1877 #pwm-cells = <3>; 1878 status = "disabled"; 1879 }; 1880 1881 pwm2_8ch_7: pwm@20f70000 { 1882 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1883 reg = <0x20f70000 0x1000>; 1884 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1885 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; 1886 clock-names = "pwm", "pclk", "osc"; 1887 pinctrl-names = "active"; 1888 pinctrl-0 = <&pwm2m0_ch7_pins>; 1889 #pwm-cells = <3>; 1890 status = "disabled"; 1891 }; 1892 1893 pwm3_8ch_0: pwm@21000000 { 1894 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1895 reg = <0x21000000 0x1000>; 1896 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1897 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1898 clock-names = "pwm", "pclk"; 1899 pinctrl-names = "active"; 1900 pinctrl-0 = <&pwm3m0_ch0_pins>; 1901 #pwm-cells = <3>; 1902 status = "disabled"; 1903 }; 1904 1905 pwm3_8ch_1: pwm@21010000 { 1906 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1907 reg = <0x21010000 0x1000>; 1908 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1909 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1910 clock-names = "pwm", "pclk"; 1911 pinctrl-names = "active"; 1912 pinctrl-0 = <&pwm3m0_ch1_pins>; 1913 #pwm-cells = <3>; 1914 status = "disabled"; 1915 }; 1916 1917 pwm3_8ch_2: pwm@21020000 { 1918 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1919 reg = <0x21020000 0x1000>; 1920 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1921 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1922 clock-names = "pwm", "pclk"; 1923 pinctrl-names = "active"; 1924 pinctrl-0 = <&pwm3m0_ch2_pins>; 1925 #pwm-cells = <3>; 1926 status = "disabled"; 1927 }; 1928 1929 pwm3_8ch_3: pwm@21030000 { 1930 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1931 reg = <0x21030000 0x1000>; 1932 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1933 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1934 clock-names = "pwm", "pclk"; 1935 pinctrl-names = "active"; 1936 pinctrl-0 = <&pwm3m0_ch3_pins>; 1937 #pwm-cells = <3>; 1938 status = "disabled"; 1939 }; 1940 1941 pwm3_8ch_4: pwm@21040000 { 1942 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1943 reg = <0x21040000 0x1000>; 1944 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1945 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1946 clock-names = "pwm", "pclk"; 1947 pinctrl-names = "active"; 1948 pinctrl-0 = <&pwm3m0_ch4_pins>; 1949 #pwm-cells = <3>; 1950 status = "disabled"; 1951 }; 1952 1953 pwm3_8ch_5: pwm@21050000 { 1954 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1955 reg = <0x21050000 0x1000>; 1956 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1958 clock-names = "pwm", "pclk"; 1959 pinctrl-names = "active"; 1960 pinctrl-0 = <&pwm3m0_ch5_pins>; 1961 #pwm-cells = <3>; 1962 status = "disabled"; 1963 }; 1964 1965 pwm3_8ch_6: pwm@21060000 { 1966 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1967 reg = <0x21060000 0x1000>; 1968 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1969 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1970 clock-names = "pwm", "pclk"; 1971 pinctrl-names = "active"; 1972 pinctrl-0 = <&pwm3m0_ch6_pins>; 1973 #pwm-cells = <3>; 1974 status = "disabled"; 1975 }; 1976 1977 pwm3_8ch_7: pwm@21070000 { 1978 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; 1979 reg = <0x21070000 0x1000>; 1980 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1981 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1982 clock-names = "pwm", "pclk"; 1983 pinctrl-names = "active"; 1984 pinctrl-0 = <&pwm3m0_ch7_pins>; 1985 #pwm-cells = <3>; 1986 status = "disabled"; 1987 }; 1988 1989 i2c0: i2c@21100000 { 1990 compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; 1991 reg = <0x21100000 0x1000>; 1992 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1996 clock-names = "i2c", "pclk"; 1997 dmas = <&dmac 29>, <&dmac 28>; 1998 dma-names = "tx", "rx"; 1999 pinctrl-names = "default"; 2000 pinctrl-0 = <&i2c0m0_pins>; 2001 status = "disabled"; 2002 }; 2003 2004 i2c1: i2c@21110000 { 2005 compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; 2006 reg = <0x21110000 0x1000>; 2007 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2008 #address-cells = <1>; 2009 #size-cells = <0>; 2010 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2011 clock-names = "i2c", "pclk"; 2012 dmas = <&dmac 31>, <&dmac 30>; 2013 dma-names = "tx", "rx"; 2014 pinctrl-names = "default"; 2015 pinctrl-0 = <&i2c1m0_pins>; 2016 status = "disabled"; 2017 }; 2018 2019 i2c3: i2c@21120000 { 2020 compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; 2021 reg = <0x21120000 0x1000>; 2022 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2023 #address-cells = <1>; 2024 #size-cells = <0>; 2025 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2026 clock-names = "i2c", "pclk"; 2027 dmas = <&dmac 35>, <&dmac 34>; 2028 dma-names = "tx", "rx"; 2029 pinctrl-names = "default"; 2030 pinctrl-0 = <&i2c3m0_pins>; 2031 status = "disabled"; 2032 }; 2033 2034 i2c4: i2c@21130000 { 2035 compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; 2036 reg = <0x21130000 0x1000>; 2037 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2041 clock-names = "i2c", "pclk"; 2042 dmas = <&dmac 37>, <&dmac 36>; 2043 dma-names = "tx", "rx"; 2044 pinctrl-names = "default"; 2045 pinctrl-0 = <&i2c4m0_pins>; 2046 status = "disabled"; 2047 }; 2048 2049 i2c5: i2c@21140000 { 2050 compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; 2051 reg = <0x21140000 0x1000>; 2052 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2053 #address-cells = <1>; 2054 #size-cells = <0>; 2055 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2056 clock-names = "i2c", "pclk"; 2057 dmas = <&dmac 39>, <&dmac 38>; 2058 dma-names = "tx", "rx"; 2059 pinctrl-names = "default"; 2060 pinctrl-0 = <&i2c5m0_pins>; 2061 status = "disabled"; 2062 }; 2063 2064 uart1: serial@21160000 { 2065 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2066 reg = <0x21160000 0x100>; 2067 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 2068 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2069 clock-names = "baudclk", "apb_pclk"; 2070 reg-shift = <2>; 2071 reg-io-width = <4>; 2072 dmas = <&dmac 3>, <&dmac 2>; 2073 pinctrl-names = "default"; 2074 pinctrl-0 = <&uart1m0_xfer_pins &uart1m0_ctsn_pins &uart1m0_rtsn_pins>; 2075 status = "disabled"; 2076 }; 2077 2078 uart2: serial@21170000 { 2079 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2080 reg = <0x21170000 0x100>; 2081 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 2082 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2083 clock-names = "baudclk", "apb_pclk"; 2084 reg-shift = <2>; 2085 reg-io-width = <4>; 2086 dmas = <&dmac 5>, <&dmac 4>; 2087 pinctrl-names = "default"; 2088 pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins &uart2m0_rtsn_pins>; 2089 status = "disabled"; 2090 }; 2091 2092 uart3: serial@21180000 { 2093 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2094 reg = <0x21180000 0x100>; 2095 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2096 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2097 clock-names = "baudclk", "apb_pclk"; 2098 reg-shift = <2>; 2099 reg-io-width = <4>; 2100 dmas = <&dmac 7>, <&dmac 6>; 2101 pinctrl-names = "default"; 2102 pinctrl-0 = <&uart3m0_xfer_pins &uart3m0_ctsn_pins &uart3m0_rtsn_pins>; 2103 status = "disabled"; 2104 }; 2105 2106 uart4: serial@21190000 { 2107 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2108 reg = <0x21190000 0x100>; 2109 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 2110 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2111 clock-names = "baudclk", "apb_pclk"; 2112 reg-shift = <2>; 2113 reg-io-width = <4>; 2114 dmas = <&dmac 9>, <&dmac 8>; 2115 pinctrl-names = "default"; 2116 pinctrl-0 = <&uart4m0_xfer_pins &uart4m0_ctsn_pins &uart4m0_rtsn_pins>; 2117 status = "disabled"; 2118 }; 2119 2120 uart5: serial@211a0000 { 2121 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2122 reg = <0x211a0000 0x100>; 2123 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 2124 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2125 clock-names = "baudclk", "apb_pclk"; 2126 reg-shift = <2>; 2127 reg-io-width = <4>; 2128 dmas = <&dmac 11>, <&dmac 10>; 2129 pinctrl-names = "default"; 2130 pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>; 2131 status = "disabled"; 2132 }; 2133 2134 uart6: serial@211b0000 { 2135 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2136 reg = <0x211b0000 0x100>; 2137 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 2138 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2139 clock-names = "baudclk", "apb_pclk"; 2140 reg-shift = <2>; 2141 reg-io-width = <4>; 2142 dmas = <&dmac 13>, <&dmac 12>; 2143 pinctrl-names = "default"; 2144 pinctrl-0 = <&uart6m0_xfer_pins &uart6m0_ctsn_pins &uart6m0_rtsn_pins>; 2145 status = "disabled"; 2146 }; 2147 2148 uart7: serial@211c0000 { 2149 compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; 2150 reg = <0x211c0000 0x100>; 2151 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 2152 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2153 clock-names = "baudclk", "apb_pclk"; 2154 reg-shift = <2>; 2155 reg-io-width = <4>; 2156 dmas = <&dmac 15>, <&dmac 14>; 2157 pinctrl-names = "default"; 2158 pinctrl-0 = <&uart7m0_xfer_pins &uart7m0_ctsn_pins &uart7m0_rtsn_pins>; 2159 status = "disabled"; 2160 }; 2161 2162 spi0: spi@211e0000 { 2163 compatible = "rockchip,rv1126b-spi", "rockchip,rk3066-spi"; 2164 reg = <0x211e0000 0x1000>; 2165 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2166 #address-cells = <1>; 2167 #size-cells = <0>; 2168 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2169 clock-names = "spiclk", "apb_pclk"; 2170 dmas = <&dmac 40>, <&dmac 41>; 2171 dma-names = "rx", "tx"; 2172 pinctrl-names = "default"; 2173 pinctrl-0 = <&spi0m0_clk_pins &spi0m0_csn0_pins &spi0m0_csn1_pins>; 2174 status = "disabled"; 2175 }; 2176 2177 spi1: spi@211f0000 { 2178 compatible = "rockchip,rv1126b-spi", "rockchip,rk3066-spi"; 2179 reg = <0x211f0000 0x1000>; 2180 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2181 #address-cells = <1>; 2182 #size-cells = <0>; 2183 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2184 clock-names = "spiclk", "apb_pclk"; 2185 dmas = <&dmac 42>, <&dmac 43>; 2186 dma-names = "rx", "tx"; 2187 pinctrl-names = "default"; 2188 pinctrl-0 = <&spi1m0_clk_pins &spi1m0_csn0_pins &spi1m0_csn1_pins>; 2189 status = "disabled"; 2190 }; 2191 2192 gic: interrupt-controller@21201000 { 2193 compatible = "arm,gic-400"; 2194 #interrupt-cells = <3>; 2195 #address-cells = <0>; 2196 interrupt-controller; 2197 reg = <0x21201000 0x1000>, 2198 <0x21202000 0x2000>, 2199 <0x21204000 0x2000>, 2200 <0x21206000 0x2000>; 2201 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2202 }; 2203 2204 hwlock: hwspinlock@21210000 { 2205 compatible = "rockchip,hwspinlock"; 2206 reg = <0x21210000 0x100>; 2207 #hwlock-cells = <1>; 2208 rockchip,hwlock-num-locks = <64>; 2209 status = "disabled"; 2210 }; 2211 2212 rtc: rtc@21280000 { 2213 compatible = "rockchip,rv1126b-rtc"; 2214 reg = <0x21280000 0x1000>; 2215 rockchip,grf = <&grf>; 2216 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 2217 clocks = <&cru PCLK_RTC_ROOT>; 2218 clock-names = "pclk_phy"; 2219 assigned-clocks = <&cru PCLK_RTC_ROOT>; 2220 assigned-clock-rates = <50000000>; 2221 status = "disabled"; 2222 }; 2223 2224 usb2phy: usb2-phy@21400000 { 2225 compatible = "rockchip,rv1126b-usb2phy"; 2226 reg = <0x21400000 0x10000>; 2227 clocks = <&cru PCLK_USB2PHY>; 2228 clock-names = "pclk"; 2229 clock-output-names = "usb480m_phy"; 2230 #clock-cells = <0>; 2231 rockchip,usbctrl-grf = <&grf>; 2232 rockchip,usbgrf = <&grf>; 2233 status = "disabled"; 2234 2235 usb2phy_host: host-port { 2236 #phy-cells = <0>; 2237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2238 interrupt-names = "linestate"; 2239 status = "disabled"; 2240 }; 2241 2242 usb2phy_otg: otg-port { 2243 #phy-cells = <0>; 2244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2247 interrupt-names = "otg-id", "otg-bvalid", "linestate"; 2248 status = "disabled"; 2249 }; 2250 }; 2251 2252 usb3phy: usb3-phy@21410000 { 2253 compatible = "rockchip,rv1126b-usb3-phy"; 2254 reg = <0x21410000 0x10000>; 2255 clocks = <&cru CLK_REF_PIPEPHY>, <&cru PCLK_PIPEPHY>; 2256 clock-names = "refclk", "apbclk"; 2257 assigned-clocks = <&cru CLK_REF_PIPEPHY>; 2258 assigned-clock-rates = <100000000>; 2259 #phy-cells = <1>; 2260 resets = <&cru SRST_PRESETN_PIPEPHY>, <&cru SRST_RESETN_REF_PIPEPHY>; 2261 reset-names = "combphy-apb", "combphy"; 2262 rockchip,pipe-grf = <&grf>; 2263 rockchip,pipe-phy-grf = <&grf>; 2264 status = "disabled"; 2265 }; 2266 2267 fspi0: spi@21460000 { 2268 compatible = "rockchip,rv1126b-fspi", "rockchip,fspi"; 2269 reg = <0x21460000 0x4000>; 2270 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2271 clocks = <&cru SCLK_2X_FSPI0>, <&cru HCLK_FSPI0>; 2272 clock-names = "clk_sfc", "hclk_sfc"; 2273 rockchip,grf = <&grf>; 2274 rockchip,max-dll = <0xFF>; 2275 #address-cells = <1>; 2276 #size-cells = <0>; 2277 status = "disabled"; 2278 }; 2279 2280 emmc: mmc@21470000 { 2281 compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc"; 2282 reg = <0x21470000 0x4000>; 2283 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2284 clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>; 2285 clock-names = "biu", "ciu"; 2286 fifo-depth = <0x100>; 2287 max-frequency = <200000000>; 2288 status = "disabled"; 2289 }; 2290 2291 usb_host_ehci: usb@21480000 { 2292 compatible = "generic-ehci"; 2293 reg = <0x21480000 0x40000>; 2294 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 2295 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_ARB_USB2HOST>, <&usb2phy>; 2296 clock-names = "usbhost", "arbiter", "utmi"; 2297 phys = <&usb2phy_host>; 2298 phy-names = "usb2-phy"; 2299 status = "disabled"; 2300 }; 2301 2302 usb_host_ohci: usb@214c0000 { 2303 compatible = "generic-ohci"; 2304 reg = <0x214c0000 0x40000>; 2305 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2306 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_ARB_USB2HOST>, <&usb2phy>; 2307 clock-names = "usbhost", "arbiter", "utmi"; 2308 phys = <&usb2phy_host>; 2309 phy-names = "usb2-phy"; 2310 status = "disabled"; 2311 }; 2312 2313 usb_drd_dwc3: usb@21500000 { 2314 compatible = "rockchip,rv1126b-dwc3", "rockchip,rk3576-dwc3", "snps,dwc3"; 2315 reg = <0x21500000 0x100000>; 2316 clocks = <&cru CLK_REF_USB3OTG>, 2317 <&cru CLK_SUSPEND_USB3OTG>, 2318 <&cru ACLK_USB3OTG>; 2319 clock-names = "ref", "suspend", "bus_clk"; 2320 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 2321 resets = <&cru SRST_ARESETN_USB3OTG>; 2322 reset-names = "usb3-otg"; 2323 dr_mode = "otg"; 2324 phys = <&usb2phy_otg>, <&usb3phy PHY_TYPE_USB3>; 2325 phy-names = "usb2-phy", "usb3-phy"; 2326 phy_type = "utmi_wide"; 2327 snps,dis_enblslpm_quirk; 2328 snps,dis-u1-entry-quirk; 2329 snps,dis-u2-entry-quirk; 2330 snps,dis-u2-freeclk-exists-quirk; 2331 snps,dis-del-phy-power-chg-quirk; 2332 snps,dis-tx-ipgap-linecheck-quirk; 2333 snps,dis_rxdet_inp3_quirk; 2334 snps,parkmode-disable-hs-quirk; 2335 snps,parkmode-disable-ss-quirk; 2336 status = "disabled"; 2337 }; 2338 2339 dfi: dfi@21620000 { 2340 compatible = "rockchip,rv1126b-dfi"; 2341 reg = <0x21620000 0x10000>; 2342 rockchip,pmugrf = <&grf>; 2343 status = "disabled"; 2344 }; 2345 2346 mipi0_csi2_hw: mipi0-csi2-hw@21c00000 { 2347 compatible = "rockchip,rv1126b-mipi-csi2-hw"; 2348 reg = <0x21c00000 0x10000>; 2349 reg-names = "csihost_regs"; 2350 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2352 interrupt-names = "csi-intr1", "csi-intr2"; 2353 clocks = <&cru PCLK_CSI2HOST0>, <&cru DCLK_CSI2HOST0>; 2354 clock-names = "pclk_csi2host", "dclk_csi2host"; 2355 resets = <&cru SRST_PRESETN_CSI2HOST0>; 2356 reset-names = "srst_csihost_p"; 2357 status = "okay"; 2358 }; 2359 2360 mipi1_csi2_hw: mipi1-csi2-hw@21c10000 { 2361 compatible = "rockchip,rv1126b-mipi-csi2-hw"; 2362 reg = <0x21c10000 0x10000>; 2363 reg-names = "csihost_regs"; 2364 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2366 interrupt-names = "csi-intr1", "csi-intr2"; 2367 clocks = <&cru PCLK_CSI2HOST1>, <&cru DCLK_CSI2HOST1>; 2368 clock-names = "pclk_csi2host", "dclk_csi2host"; 2369 resets = <&cru SRST_PRESETN_CSI2HOST1>; 2370 reset-names = "srst_csihost_p"; 2371 status = "okay"; 2372 }; 2373 2374 mipi2_csi2_hw: mipi2-csi2-hw@21c20000 { 2375 compatible = "rockchip,rv1126b-mipi-csi2-hw"; 2376 reg = <0x21c20000 0x10000>; 2377 reg-names = "csihost_regs"; 2378 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2380 interrupt-names = "csi-intr1", "csi-intr2"; 2381 clocks = <&cru PCLK_CSI2HOST2>, <&cru DCLK_CSI2HOST2>; 2382 clock-names = "pclk_csi2host", "dclk_csi2host"; 2383 resets = <&cru SRST_PRESETN_CSI2HOST2>; 2384 reset-names = "srst_csihost_p"; 2385 status = "okay"; 2386 }; 2387 2388 mipi3_csi2_hw: mipi3-csi2-hw@21c30000 { 2389 compatible = "rockchip,rv1126b-mipi-csi2-hw"; 2390 reg = <0x21c30000 0x10000>; 2391 reg-names = "csihost_regs"; 2392 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2394 interrupt-names = "csi-intr1", "csi-intr2"; 2395 clocks = <&cru PCLK_CSI2HOST3>, <&cru DCLK_CSI2HOST3>; 2396 clock-names = "pclk_csi2host", "dclk_csi2host"; 2397 resets = <&cru SRST_PRESETN_CSI2HOST3>; 2398 reset-names = "srst_csihost_p"; 2399 status = "okay"; 2400 }; 2401 2402 csi2_dphy0_hw: csi2-dphy0-hw@21c40000 { 2403 compatible = "rockchip,rv1126b-csi2-dphy-hw"; 2404 reg = <0x21c40000 0x10000>; 2405 clocks = <&cru PCLK_CSIPHY0>; 2406 clock-names = "pclk"; 2407 resets = <&cru SRST_PRESETN_CSIPHY0>; 2408 reset-names = "srst_p_csiphy0"; 2409 rockchip,grf = <&grf>; 2410 status = "okay"; 2411 }; 2412 2413 csi2_dphy1_hw: csi2-dphy1-hw@21c50000 { 2414 compatible = "rockchip,rv1126b-csi2-dphy-hw"; 2415 reg = <0x21c50000 0x10000>; 2416 clocks = <&cru PCLK_CSIPHY1>; 2417 clock-names = "pclk"; 2418 resets = <&cru SRST_PRESETN_CSIPHY1>; 2419 reset-names = "srst_p_csiphy1"; 2420 rockchip,grf = <&grf>; 2421 status = "okay"; 2422 }; 2423 2424 gmac: ethernet@21c70000 { 2425 compatible = "rockchip,rv1126b-gmac", "snps,dwmac-4.20a"; 2426 reg = <0x21c70000 0x10000>; 2427 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 2429 interrupt-names = "macirq", "eth_wake_irq"; 2430 rockchip,grf = <&grf>; 2431 rockchip,php_grf = <&ioc_grf>; 2432 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_50M_GMAC_IOBUF_VI>, 2433 <&cru PCLK_GMAC>, <&cru ACLK_GMAC>, 2434 <&cru CLK_GMAC_PTP_REF>; 2435 clock-names = "stmmaceth", "clk_mac_ref", 2436 "pclk_mac", "aclk_mac", 2437 "ptp_ref"; 2438 resets = <&cru SRST_ARESETN_GMAC>; 2439 reset-names = "stmmaceth"; 2440 2441 snps,mixed-burst; 2442 snps,tso; 2443 2444 snps,axi-config = <&gmac0_stmmac_axi_setup>; 2445 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 2446 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 2447 status = "disabled"; 2448 2449 mdio: mdio { 2450 compatible = "snps,dwmac-mdio"; 2451 #address-cells = <0x1>; 2452 #size-cells = <0x0>; 2453 }; 2454 2455 gmac0_stmmac_axi_setup: stmmac-axi-config { 2456 snps,wr_osr_lmt = <4>; 2457 snps,rd_osr_lmt = <8>; 2458 snps,blen = <0 0 0 0 16 8 4>; 2459 }; 2460 2461 gmac0_mtl_rx_setup: rx-queues-config { 2462 snps,rx-queues-to-use = <1>; 2463 queue0 { 2464 status = "okay"; 2465 }; 2466 }; 2467 2468 gmac0_mtl_tx_setup: tx-queues-config { 2469 snps,tx-queues-to-use = <1>; 2470 queue0 { 2471 status = "okay"; 2472 }; 2473 }; 2474 }; 2475 2476 dsmc: dsmc@21ca0000 { 2477 compatible = "rockchip,rv1126b-dsmc", "rockchip,rk3506-dsmc"; 2478 reg = <0x21ca0000 0x10000>; 2479 rockchip,grf = <&grf>; 2480 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2481 resets = <&cru SRST_ARESETN_DSMC>, <&cru SRST_PRESETN_DSMC>; 2482 reset-names = "dsmc", "apb"; 2483 clocks = <&cru CLK_SYS_DSMC_ROOT>, 2484 <&cru ACLK_DSMC>, 2485 <&cru PCLK_DSMC>, 2486 <&cru CLK_SYS_DSMC_ROOT>; 2487 clock-names = "clk_sys", "aclk_dsmc", "pclk", "aclk_root"; 2488 clock-frequency = <100000000>; 2489 dmas = <&dmac 46>, <&dmac 47>; 2490 dma-names = "req0", "req1"; 2491 pinctrl-names = "default", "active", "lb-slave"; 2492 pinctrl-0 = <&dsmc_csn_idle 2493 &dsmc_bus16_pins 2494 &dsmc_clk_pins>; 2495 pinctrl-1 = <&dsmc_csn_pins>; 2496 pinctrl-2 = <&dsmc_int_pins>; 2497 status = "disabled"; 2498 slave { 2499 rockchip,dqs-dll = <0x20 0x20 2500 0x20 0x20 2501 0x20 0x20 2502 0x20 0x20>; 2503 rockchip,ranges = <0x0 0x10000000 0x0 0x2000000>; 2504 rockchip,slave-dev = <&dsmc_slave>; 2505 }; 2506 }; 2507 2508 dsmc_slave: dsmc-slave { 2509 compatible = "rockchip,dsmc-slave"; 2510 rockchip,clk-mode = <0>; 2511 status = "disabled"; 2512 psram { 2513 dsmc_psram0: psram0 { 2514 status = "disabled"; 2515 }; 2516 dsmc_psram1: psram1 { 2517 status = "disabled"; 2518 }; 2519 dsmc_psram2: psram2 { 2520 status = "disabled"; 2521 }; 2522 dsmc_psram3: psram3 { 2523 status = "disabled"; 2524 }; 2525 }; 2526 2527 lb-slave { 2528 dsmc_lb_slave0: lb-slave0 { 2529 rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; 2530 rockchip,int-en = <0x0>; 2531 status = "disabled"; 2532 dsmc_p0_region: region { 2533 dsmc_p0_region0: region0 { 2534 rockchip,attribute = "Merged FIFO"; 2535 rockchip,ca-addr-width = <0>; 2536 rockchip,dummy-clk-num = <1>; 2537 rockchip,cs0-be-ctrled = <0>; 2538 rockchip,cs0-ctrl = <0>; 2539 status = "disabled"; 2540 }; 2541 dsmc_p0_region1: region1 { 2542 rockchip,attribute = "No-Merge FIFO"; 2543 rockchip,ca-addr-width = <0>; 2544 rockchip,dummy-clk-num = <1>; 2545 rockchip,cs0-be-ctrled = <0>; 2546 rockchip,cs0-ctrl = <0>; 2547 status = "disabled"; 2548 }; 2549 dsmc_p0_region2: region2 { 2550 rockchip,attribute = "DPRA"; 2551 rockchip,ca-addr-width = <0>; 2552 rockchip,dummy-clk-num = <1>; 2553 rockchip,cs0-be-ctrled = <0>; 2554 rockchip,cs0-ctrl = <0>; 2555 status = "disabled"; 2556 }; 2557 dsmc_p0_region3: region3 { 2558 rockchip,attribute = "Register"; 2559 rockchip,ca-addr-width = <0>; 2560 rockchip,dummy-clk-num = <1>; 2561 rockchip,cs0-be-ctrled = <0>; 2562 rockchip,cs0-ctrl = <0>; 2563 status = "disabled"; 2564 }; 2565 }; 2566 }; 2567 dsmc_lb_slave1: lb-slave1 { 2568 rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; 2569 rockchip,int-en = <0x1>; 2570 status = "disabled"; 2571 dsmc_p1_region: region { 2572 dsmc_p1_region0: region0 { 2573 rockchip,attribute = "Merged FIFO"; 2574 rockchip,ca-addr-width = <0>; 2575 rockchip,dummy-clk-num = <1>; 2576 rockchip,cs0-be-ctrled = <0>; 2577 rockchip,cs0-ctrl = <0>; 2578 status = "disabled"; 2579 }; 2580 dsmc_p1_region1: region1 { 2581 rockchip,attribute = "No-Merge FIFO"; 2582 rockchip,ca-addr-width = <0>; 2583 rockchip,dummy-clk-num = <1>; 2584 rockchip,cs0-be-ctrled = <0>; 2585 rockchip,cs0-ctrl = <0>; 2586 status = "disabled"; 2587 }; 2588 dsmc_p1_region2: region2 { 2589 rockchip,attribute = "DPRA"; 2590 rockchip,ca-addr-width = <0>; 2591 rockchip,dummy-clk-num = <1>; 2592 rockchip,cs0-be-ctrled = <0>; 2593 rockchip,cs0-ctrl = <0>; 2594 status = "disabled"; 2595 }; 2596 dsmc_p1_region3: region3 { 2597 rockchip,attribute = "Register"; 2598 rockchip,ca-addr-width = <0>; 2599 rockchip,dummy-clk-num = <1>; 2600 rockchip,cs0-be-ctrled = <0>; 2601 rockchip,cs0-ctrl = <0>; 2602 status = "disabled"; 2603 }; 2604 }; 2605 }; 2606 dsmc_lb_slave2: lb-slave2 { 2607 rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; 2608 rockchip,int-en = <0x2>; 2609 status = "disabled"; 2610 dsmc_p2_region: region { 2611 dsmc_p2_region0: region0 { 2612 rockchip,attribute = "Merged FIFO"; 2613 rockchip,ca-addr-width = <0>; 2614 rockchip,dummy-clk-num = <1>; 2615 rockchip,cs0-be-ctrled = <0>; 2616 rockchip,cs0-ctrl = <0>; 2617 status = "disabled"; 2618 }; 2619 dsmc_p2_region1: region1 { 2620 rockchip,attribute = "No-Merge FIFO"; 2621 rockchip,ca-addr-width = <0>; 2622 rockchip,dummy-clk-num = <1>; 2623 rockchip,cs0-be-ctrled = <0>; 2624 rockchip,cs0-ctrl = <0>; 2625 status = "disabled"; 2626 }; 2627 dsmc_p2_region2: region2 { 2628 rockchip,attribute = "DPRA"; 2629 rockchip,ca-addr-width = <0>; 2630 rockchip,dummy-clk-num = <1>; 2631 rockchip,cs0-be-ctrled = <0>; 2632 rockchip,cs0-ctrl = <0>; 2633 status = "disabled"; 2634 }; 2635 dsmc_p2_region3: region3 { 2636 rockchip,attribute = "Register"; 2637 rockchip,ca-addr-width = <0>; 2638 rockchip,dummy-clk-num = <1>; 2639 rockchip,cs0-be-ctrled = <0>; 2640 rockchip,cs0-ctrl = <0>; 2641 status = "disabled"; 2642 }; 2643 }; 2644 }; 2645 dsmc_lb_slave3: lb-slave3 { 2646 rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; 2647 rockchip,int-en = <0x3>; 2648 status = "disabled"; 2649 dsmc_p3_region: region { 2650 dsmc_p3_region0: region0 { 2651 rockchip,attribute = "Merged FIFO"; 2652 rockchip,ca-addr-width = <0>; 2653 rockchip,dummy-clk-num = <1>; 2654 rockchip,cs0-be-ctrled = <0>; 2655 rockchip,cs0-ctrl = <0>; 2656 status = "disabled"; 2657 }; 2658 dsmc_p3_region1: region1 { 2659 rockchip,attribute = "No-Merge FIFO"; 2660 rockchip,ca-addr-width = <0>; 2661 rockchip,dummy-clk-num = <1>; 2662 rockchip,cs0-be-ctrled = <0>; 2663 rockchip,cs0-ctrl = <0>; 2664 status = "disabled"; 2665 }; 2666 dsmc_p3_region2: region2 { 2667 rockchip,attribute = "DPRA"; 2668 rockchip,ca-addr-width = <0>; 2669 rockchip,dummy-clk-num = <1>; 2670 rockchip,cs0-be-ctrled = <0>; 2671 rockchip,cs0-ctrl = <0>; 2672 status = "disabled"; 2673 }; 2674 dsmc_p3_region3: region3 { 2675 rockchip,attribute = "Register"; 2676 rockchip,ca-addr-width = <0>; 2677 rockchip,dummy-clk-num = <1>; 2678 rockchip,cs0-be-ctrled = <0>; 2679 rockchip,cs0-ctrl = <0>; 2680 status = "disabled"; 2681 }; 2682 }; 2683 }; 2684 }; 2685 }; 2686 2687 saradc1: saradc@21cb0000 { 2688 compatible = "rockchip,rv1126b-saradc"; 2689 reg = <0x21cb0000 0x10000>; 2690 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 2691 #io-channel-cells = <1>; 2692 clocks = <&cru CLK_SARADC1>, <&cru PCLK_SARADC1>; 2693 clock-names = "saradc", "apb_pclk"; 2694 resets = <&cru SRST_PRESETN_SARADC1>; 2695 reset-names = "saradc-apb"; 2696 status = "disabled"; 2697 }; 2698 2699 saradc2: saradc@21cc0000 { 2700 compatible = "rockchip,rv1126b-saradc"; 2701 reg = <0x21cc0000 0x10000>; 2702 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 2703 #io-channel-cells = <1>; 2704 clocks = <&cru CLK_SARADC2>, <&cru PCLK_SARADC2>; 2705 clock-names = "saradc", "apb_pclk"; 2706 resets = <&cru SRST_PRESETN_SARADC2>; 2707 reset-names = "saradc-apb"; 2708 status = "disabled"; 2709 }; 2710 2711 rkisp: isp@21d00000 { 2712 compatible = "rockchip,rv1126b-rkisp"; 2713 reg = <0x21d00000 0x7f00>, <0x21d30000 0x2f00>; 2714 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2719 interrupt-names = "isp_mipi_irq", "isp_mi_irq", "isp_irq", 2720 "vpsl_mi_irq", "vpsl_irq"; 2721 clocks = <&cru HCLK_ISP>, <&cru ACLK_ISP>, 2722 <&cru CLK_CORE_ISP>, <&cru ISP0CLK_VICAP>, 2723 <&cru HCLK_VPSL>, <&cru ACLK_VPSL>, <&cru CLK_CORE_VPSL>; 2724 clock-names = "hclk_isp", "aclk_isp", 2725 "clk_isp_core", "clk_isp_vicap", 2726 "hclk_vpsl", "aclk_vpsl", "clk_core_vpsl"; 2727 iommus = <&rkisp_mmu>; 2728 status = "disabled"; 2729 }; 2730 2731 rkisp_mmu: iommu@21d07f00 { 2732 compatible = "rockchip,iommu-v2"; 2733 reg = <0x21d07f00 0x100>, <0x21d32f00 0x100>; 2734 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2735 interrupt-names = "isp_mmu", "vpsl_mmu"; 2736 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 2737 <&cru ACLK_VPSL>, <&cru HCLK_VPSL>; 2738 clock-names = "aclk0", "iface0", "aclk1", "iface1"; 2739 #iommu-cells = <0>; 2740 rockchip,disable-mmu-reset; 2741 status = "disabled"; 2742 }; 2743 2744 rkcif: rkcif@21d10000 { 2745 compatible = "rockchip,rv1126b-cif"; 2746 reg = <0x21d10000 0x1000>; 2747 reg-names = "cif_regs"; 2748 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2749 interrupt-names = "cif-intr"; 2750 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 2751 <&cru DCLK_VICAP>, <&cru ISP0CLK_VICAP>; 2752 clock-names = "aclk_cif", "hclk_cif", 2753 "dclk_cif", "isp0clk_cif"; 2754 resets = <&cru SRST_ARESETN_VICAP>, <&cru SRST_HRESETN_VICAP>, 2755 <&cru SRST_DRESETN_VICAP>, <&cru SRST_ISP0RESETN_VICAP>; 2756 reset-names = "rst_cif_a", "rst_cif_h", 2757 "rst_cif_d", "rst_cif_isp0"; 2758 rockchip,grf = <&grf>; 2759 iommus = <&rkcif_mmu>; 2760 status = "disabled"; 2761 }; 2762 2763 rkcif_mmu: iommu@21d10f00 { 2764 compatible = "rockchip,iommu-v2"; 2765 reg = <0x21d10f00 0x100>; 2766 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2767 interrupt-names = "cif_mmu"; 2768 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 2769 clock-names = "aclk", "iface"; 2770 rockchip,disable-mmu-reset; 2771 #iommu-cells = <0>; 2772 status = "disabled"; 2773 }; 2774 2775 rkvpss: vpss@21d20000 { 2776 compatible = "rockchip,rv1126b-rkvpss"; 2777 reg = <0x21d20000 0x3f00>; 2778 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2780 interrupt-names = "mi_irq", "vpss_irq"; 2781 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>, 2782 <&cru CLK_CORE_VPSS>; 2783 clock-names = "aclk_vpss", "hclk_vpss", "clk_vpss"; 2784 iommus = <&rkvpss_mmu>; 2785 status = "disabled"; 2786 }; 2787 2788 rkvpss_mmu: iommu@21d23f00 { 2789 compatible = "rockchip,iommu-v2"; 2790 reg = <0x21d23f00 0x100>; 2791 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2792 interrupt-names = "vpss_mmu"; 2793 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>; 2794 clock-names = "aclk", "iface"; 2795 #iommu-cells = <0>; 2796 rockchip,disable-mmu-reset; 2797 status = "disabled"; 2798 }; 2799 2800 can0: can@21d40000 { 2801 compatible = "rockchip,rv1126b-canfd"; 2802 reg = <0x21d40000 0x1000>; 2803 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 2804 clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>; 2805 clock-names = "baudclk", "apb_pclk"; 2806 resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_HRESETN_CAN0>; 2807 reset-names = "can", "can-apb"; 2808 dmas = <&dmac 44>; 2809 dma-names = "rx"; 2810 status = "disabled"; 2811 }; 2812 2813 can1: can@21d50000 { 2814 compatible = "rockchip,rv1126b-canfd"; 2815 reg = <0x21d50000 0x1000>; 2816 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 2817 clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>; 2818 clock-names = "baudclk", "apb_pclk"; 2819 resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_HRESETN_CAN1>; 2820 reset-names = "can", "can-apb"; 2821 dmas = <&dmac 45>; 2822 dma-names = "rx"; 2823 status = "disabled"; 2824 }; 2825 2826 sdmmc0: mmc@21d60000 { 2827 compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc"; 2828 reg = <0x21d60000 0x4000>; 2829 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2830 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>; 2831 clock-names = "biu", "ciu"; 2832 fifo-depth = <0x100>; 2833 max-frequency = <200000000>; 2834 pinctrl-names = "normal", "idle"; 2835 pinctrl-0 = <&sdmmc0_clk_pins &sdmmc0_cmd_pins &sdmmc0_detn_pins &sdmmc0_bus4_pins>; 2836 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_detn_pins>; 2837 status = "disabled"; 2838 }; 2839 2840 saradc0: saradc@21f10000 { 2841 compatible = "rockchip,rv1126b-saradc"; 2842 reg = <0x21f10000 0x10000>; 2843 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 2844 #io-channel-cells = <1>; 2845 clocks = <&cru CLK_SARADC0>, <&cru PCLK_SARADC0>; 2846 clock-names = "saradc", "apb_pclk"; 2847 resets = <&cru SRST_PRESETN_SARADC0>; 2848 reset-names = "saradc-apb"; 2849 status = "disabled"; 2850 }; 2851 2852 rkvenc: rkvenc@21f40000 { 2853 compatible = "rockchip,rkv-encoder-rv1126b", "rockchip,rkv-encoder-v2"; 2854 reg = <0x21f40000 0x6000>; 2855 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 2856 interrupt-names = "irq_rkvenc"; 2857 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>; 2858 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 2859 rockchip,normal-rates = <396000000>, <0>, <396000000>; 2860 resets = <&cru SRST_ARESETN_VEPU>, <&cru SRST_HRESETN_VEPU>, 2861 <&cru SRST_RESETN_CORE_VEPU>; 2862 reset-names = "video_a", "video_h", "video_core"; 2863 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>; 2864 assigned-clock-rates = <396000000>, <396000000>; 2865 iommus = <&rkvenc_mmu>; 2866 rockchip,srv = <&mpp_srv>; 2867 rockchip,taskqueue-node = <0>; 2868 rockchip,resetgroup-node = <0>; 2869 rockchip,skip-pmu-idle-request; 2870 dvbm = <&rkdvbm>; 2871 power-domains = <&power RV1126B_PD_VDO>; 2872 status = "disabled"; 2873 }; 2874 2875 rkvenc_mmu: iommu@21f4f000 { 2876 compatible = "rockchip,iommu-v2"; 2877 reg = <0x21f4f000 0x100>; 2878 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 2879 interrupt-names = "rkvenc_mmu"; 2880 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; 2881 clock-names = "aclk", "iface"; 2882 #iommu-cells = <0>; 2883 rockchip,shootdown-entire; 2884 rockchip,enable-cmd-retry; 2885 power-domains = <&power RV1126B_PD_VDO>; 2886 status = "disabled"; 2887 }; 2888 2889 sdmmc1: mmc@21f60000 { 2890 compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc"; 2891 reg = <0x21f60000 0x4000>; 2892 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2893 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>; 2894 clock-names = "biu", "ciu"; 2895 fifo-depth = <0x100>; 2896 max-frequency = <200000000>; 2897 pinctrl-names = "default"; 2898 pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_detn_pins &sdmmc1_bus4_pins>; 2899 status = "disabled"; 2900 }; 2901 2902 rkfec: rkfec@21f80000 { 2903 compatible = "rockchip,rv1126b-rkfec"; 2904 reg = <0x21f80000 0xf00>; 2905 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2906 interrupt-names = "fec_irq"; 2907 clocks = <&cru ACLK_FEC>, <&cru HCLK_FEC>, <&cru CLK_CORE_FEC>; 2908 clock-names = "aclk_fec", "hclk_fec", "clk_fec"; 2909 iommus = <&rkfec_mmu>; 2910 status = "disabled"; 2911 }; 2912 2913 rkfec_mmu: iommu@21f80f00 { 2914 compatible = "rockchip,iommu-v2"; 2915 reg = <0x21f80f00 0x100>; 2916 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 2917 interrupt-names = "fec_mmu"; 2918 clocks = <&cru ACLK_FEC>, <&cru HCLK_FEC>; 2919 clock-names = "aclk", "iface"; 2920 #iommu-cells = <0>; 2921 rockchip,disable-mmu-reset; 2922 status = "disabled"; 2923 }; 2924 2925 rkavsp: rkavsp@21f90000 { 2926 compatible = "rockchip,rv1126b-rkavsp"; 2927 reg = <0x21f90000 0xf00>; 2928 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2929 interrupt-names = "dcp_irq", "rcs_irq"; 2930 clocks = <&cru ACLK_AVSP>, <&cru HCLK_AVSP>; 2931 clock-names = "aclk_avsp", "hclk_avsp"; 2932 iommus = <&rkavsp_mmu>; 2933 status = "disabled"; 2934 }; 2935 2936 rkavsp_mmu: iommu@21f90f00 { 2937 compatible = "rockchip,iommu-v2"; 2938 reg = <0x21f90f00 0x100>; 2939 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2940 interrupt-names = "avsp_mmu"; 2941 clocks = <&cru ACLK_AVSP>, <&cru HCLK_AVSP>; 2942 clock-names = "aclk", "iface"; 2943 #iommu-cells = <0>; 2944 rockchip,disable-mmu-reset; 2945 status = "disabled"; 2946 }; 2947 2948 rkaiisp: rkaiisp@21fa0000 { 2949 compatible = "rockchip,rv1126b-rkaiisp"; 2950 reg = <0x21fa0000 0x3f00>; 2951 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 2952 interrupt-names = "irq"; 2953 clocks = <&cru ACLK_AISP>, <&cru HCLK_AISP>, 2954 <&cru CLK_CORE_AISP>; 2955 clock-names = "aclk_aiisp", "hclk_aiisp", "clk_aiisp_core"; 2956 iommus = <&rkaiisp_mmu>; 2957 power-domains = <&power RV1126B_PD_AISP>; 2958 status = "disabled"; 2959 }; 2960 2961 rkaiisp_mmu: iommu@21fa3f00 { 2962 compatible = "rockchip,iommu-v2"; 2963 reg = <0x21fa3f00 0x100>; 2964 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 2965 interrupt-names = "aiisp_mmu"; 2966 clocks = <&cru ACLK_AISP>, <&cru HCLK_AISP>; 2967 clock-names = "aclk", "iface"; 2968 power-domains = <&power RV1126B_PD_AISP>; 2969 rockchip,disable-mmu-reset; 2970 #iommu-cells = <0>; 2971 status = "disabled"; 2972 }; 2973 2974 rknpu: npu@22000000 { 2975 compatible = "rockchip,rv1126b-rknpu"; 2976 reg = <0x22000000 0x8000>; 2977 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2978 interrupt-names = "npu_irq"; 2979 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 2980 clock-names = "aclk", "hclk"; 2981 assigned-clocks = <&cru ACLK_RKNN>; 2982 assigned-clock-rates = <800000000>; 2983 operating-points-v2 = <&npu_opp_table>; 2984 resets = <&cru SRST_ARESETN_RKNN>, <&cru SRST_HRESETN_RKNN>; 2985 reset-names = "srst_a", "srst_h"; 2986 power-domains = <&power RV1126B_PD_NPU>; 2987 iommus = <&rknpu_mmu>; 2988 status = "disabled"; 2989 }; 2990 2991 npu_opp_table: npu-opp-table { 2992 compatible = "operating-points-v2"; 2993 2994 nvmem-cells = <&npu_leakage>; 2995 nvmem-cell-names = "leakage"; 2996 2997 opp-396000000 { 2998 opp-hz = /bits/ 64 <396000000>; 2999 opp-microvolt = <900000 900000 1000000>; 3000 }; 3001 opp-594000000 { 3002 opp-hz = /bits/ 64 <594000000>; 3003 opp-microvolt = <900000 900000 1000000>; 3004 }; 3005 }; 3006 3007 rknpu_mmu: iommu@22002000 { 3008 compatible = "rockchip,iommu-v2"; 3009 reg = <0x22002000 0x100>; 3010 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 3011 interrupt-names = "rknpu_mmu"; 3012 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 3013 clock-names = "aclk", "hclk"; 3014 power-domains = <&power RV1126B_PD_NPU>; 3015 #iommu-cells = <0>; 3016 status = "disabled"; 3017 }; 3018 3019 hw_decompress: decompress@22100000 { 3020 compatible = "rockchip,hw-decompress"; 3021 reg = <0x22100000 0x1000>; 3022 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3023 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 3024 clock-names = "aclk", "dclk", "pclk"; 3025 resets = <&cru SRST_DRESETN_DECOM>; 3026 reset-names = "dresetn"; 3027 status = "disabled"; 3028 }; 3029 3030 mipi_dphy: mipi-dphy@22110000 { 3031 compatible = "rockchip,rv1126b-dsi-dphy", "rockchip,rv1126-dsi-dphy"; 3032 reg = <0x22110000 0x500>, <0x22120000 0x500>; 3033 reg-names = "phy", "host"; 3034 assigned-clock-rates = <24000000>; 3035 clocks = <&xin24m>, <&cru PCLK_DSIPHY>, <&cru PCLK_MIPI_DSI>; 3036 clock-names = "ref", "pclk", "pclk_host"; 3037 #clock-cells = <0>; 3038 resets = <&cru SRST_PRESETN_DSIPHY>; 3039 reset-names = "apb"; 3040 #phy-cells = <0>; 3041 rockchip,grf = <&grf>; 3042 status = "disabled"; 3043 }; 3044 3045 dsi: dsi@22120000 { 3046 compatible = "rockchip,rv1126b-mipi-dsi"; 3047 reg = <0x22120000 0x500>; 3048 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 3049 clocks = <&cru PCLK_MIPI_DSI>; 3050 clock-names = "pclk"; 3051 resets = <&cru SRST_PRESETN_MIPI_DSI>; 3052 reset-names = "apb"; 3053 phys = <&mipi_dphy>; 3054 phy-names = "dphy"; 3055 rockchip,grf = <&grf>; 3056 #address-cells = <1>; 3057 #size-cells = <0>; 3058 power-domains = <&power RV1126B_PD_VDO>; 3059 status = "disabled"; 3060 3061 ports { 3062 port { 3063 dsi_in_vop: endpoint { 3064 remote-endpoint = <&vop_out_dsi>; 3065 }; 3066 }; 3067 }; 3068 }; 3069 3070 rkvdec: rkvdec@22140100 { 3071 compatible = "rockchip,rkv-decoder-rv1126b", "rockchip,rkv-decoder-v384a"; 3072 reg = <0x22140100 0x600>, <0x22140000 0x100>; 3073 reg-names = "regs", "link"; 3074 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 3075 interrupt-names = "irq_rkvdec"; 3076 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 3077 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_hevc_cabac"; 3078 resets = <&cru SRST_ARESETN_VDO_BIU >, <&cru SRST_HRESETN_VDO_BIU>, 3079 <&cru SRST_RESETN_HEVC_CA_RKVDEC>; 3080 reset-names = "video_a","video_h", "video_hevc_cabac"; 3081 rockchip,normal-rates = <300000000>, <0>, <300000000>; 3082 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 3083 assigned-clock-rates = <300000000>, <0>, <300000000>; 3084 iommus = <&rkvdec_mmu>; 3085 rockchip,srv = <&mpp_srv>; 3086 rockchip,task-capacity = <8>; 3087 rockchip,taskqueue-node = <1>; 3088 rockchip,resetgroup-node = <1>; 3089 rockchip,skip-pmu-idle-request; 3090 power-domains = <&power RV1126B_PD_VDO>; 3091 status = "disabled"; 3092 }; 3093 3094 rkvdec_mmu: iommu@22140800 { 3095 compatible = "rockchip,iommu-v2"; 3096 reg = <0x22140800 0x40>, <0x22140900 0x40>; 3097 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3098 interrupt-names = "irq_rkvdec_mmu"; 3099 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 3100 clock-names = "aclk", "iface", "iface_c"; 3101 rockchip,enable-cmd-retry; 3102 rockchip,shootdown-entire; 3103 #iommu-cells = <0>; 3104 power-domains = <&power RV1126B_PD_VDO>; 3105 status = "disabled"; 3106 }; 3107 3108 vop: vop@22150000 { 3109 compatible = "rockchip,rv1126b-vop"; 3110 reg = <0x22150000 0x200>, <0x22150a00 0x400>; 3111 reg-names = "regs", "gamma_lut"; 3112 rockchip,grf = <&ioc_grf>; 3113 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 3114 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 3115 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 3116 iommus = <&vop_mmu>; 3117 status = "disabled"; 3118 3119 vop_out: port { 3120 #address-cells = <1>; 3121 #size-cells = <0>; 3122 3123 vop_out_rgb: endpoint@0 { 3124 reg = <0>; 3125 remote-endpoint = <&rgb_in_vop>; 3126 }; 3127 3128 vop_out_dsi: endpoint@1 { 3129 reg = <1>; 3130 remote-endpoint = <&dsi_in_vop>; 3131 }; 3132 }; 3133 }; 3134 3135 vop_mmu: iommu@22150f00 { 3136 compatible = "rockchip,iommu-v2"; 3137 reg = <0x22150f00 0x100>; 3138 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 3139 interrupt-names = "vop_mmu"; 3140 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 3141 clock-names = "aclk", "iface"; 3142 #iommu-cells = <0>; 3143 rockchip,disable-device-link-resume; 3144 status = "disabled"; 3145 }; 3146 3147 jpegd: jpegd@22170000 { 3148 compatible = "rockchip,rkv-jpeg-decoder-v1"; 3149 reg = <0x22170000 0x330>; 3150 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3151 interrupt-names = "irq_jpegd"; 3152 clocks = <&cru ACLK_RKJPEG>, <&cru HCLK_RKJPEG>; 3153 clock-names = "aclk_vcodec", "hclk_vcodec"; 3154 rockchip,normal-rates = <400000000>, <0>; 3155 assigned-clocks = <&cru ACLK_RKJPEG>; 3156 assigned-clock-rates = <400000000>; 3157 resets = <&cru SRST_ARESETN_RKJPEG>, <&cru SRST_HRESETN_RKJPEG>; 3158 reset-names = "video_a", "video_h"; 3159 rockchip,skip-pmu-idle-request; 3160 iommus = <&jpeg_mmu>; 3161 rockchip,srv = <&mpp_srv>; 3162 rockchip,taskqueue-node = <2>; 3163 rockchip,resetgroup-node = <2>; 3164 power-domains = <&power RV1126B_PD_VDO>; 3165 status = "disabled"; 3166 }; 3167 3168 jpeg_mmu: iommu@22170f00 { 3169 compatible = "rockchip,iommu-v2"; 3170 reg = <0x22170f00 0x28>; 3171 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3172 interrupt-names = "irq_jpeg_mmu"; 3173 clocks = <&cru ACLK_RKJPEG>, <&cru HCLK_RKJPEG>; 3174 clock-name = "aclk", "iface"; 3175 #iommu-cells = <0>; 3176 rockchip,shootdown-entire; 3177 power-domains = <&power RV1126B_PD_VDO>; 3178 status = "disabled"; 3179 }; 3180 3181 decom_mmu: iommu@22180000 { 3182 compatible = "rockchip,iommu-v2"; 3183 reg = <0x22180000 0x100>; 3184 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 3185 interrupt-names = "decom_mmu"; 3186 clocks = <&cru ACLK_RKMMU_DECOM>, <&cru HCLK_RKMMU_DECOM>; 3187 clock-names = "aclk", "iface"; 3188 #iommu-cells = <0>; 3189 status = "disabled"; 3190 }; 3191 3192 system_sram: sram@3ffb0000 { 3193 compatible = "mmio-sram"; 3194 reg = <0x3ffb0000 0x10000>; 3195 #address-cells = <1>; 3196 #size-cells = <1>; 3197 ranges = <0 0x3ffb0000 0x10000>; 3198 }; 3199 3200 pinctrl: pinctrl { 3201 compatible = "rockchip,rv1126b-pinctrl"; 3202 rockchip,grf = <&ioc_grf>; 3203 #address-cells = <1>; 3204 #size-cells = <1>; 3205 ranges; 3206 3207 gpio0: gpio@20600000 { 3208 compatible = "rockchip,gpio-bank"; 3209 reg = <0x20600000 0x200>; 3210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3211 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; 3212 3213 gpio-controller; 3214 #gpio-cells = <2>; 3215 gpio-ranges = <&pinctrl 0 0 32>; 3216 interrupt-controller; 3217 #interrupt-cells = <2>; 3218 }; 3219 3220 gpio1: gpio@21300000 { 3221 compatible = "rockchip,gpio-bank"; 3222 reg = <0x21300000 0x200>; 3223 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 3224 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 3225 3226 gpio-controller; 3227 #gpio-cells = <2>; 3228 gpio-ranges = <&pinctrl 0 32 32>; 3229 interrupt-controller; 3230 #interrupt-cells = <2>; 3231 }; 3232 3233 gpio2: gpio@21700000 { 3234 compatible = "rockchip,gpio-bank"; 3235 reg = <0x21700000 0x200>; 3236 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3237 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 3238 3239 gpio-controller; 3240 #gpio-cells = <2>; 3241 gpio-ranges = <&pinctrl 0 64 32>; 3242 interrupt-controller; 3243 #interrupt-cells = <2>; 3244 }; 3245 3246 gpio3: gpio@21e00000 { 3247 compatible = "rockchip,gpio-bank"; 3248 reg = <0x21e00000 0x200>; 3249 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3250 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 3251 3252 gpio-controller; 3253 #gpio-cells = <2>; 3254 gpio-ranges = <&pinctrl 0 96 32>; 3255 interrupt-controller; 3256 #interrupt-cells = <2>; 3257 }; 3258 3259 gpio4: gpio@21800000 { 3260 compatible = "rockchip,gpio-bank"; 3261 reg = <0x21800000 0x200>; 3262 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 3263 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 3264 3265 gpio-controller; 3266 #gpio-cells = <2>; 3267 gpio-ranges = <&pinctrl 0 128 32>; 3268 interrupt-controller; 3269 #interrupt-cells = <2>; 3270 }; 3271 3272 gpio5: gpio@21900000 { 3273 compatible = "rockchip,gpio-bank"; 3274 reg = <0x21900000 0x200>; 3275 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 3276 clocks = <&cru PCLK_GPIO5>, <&cru DBCLK_GPIO5>; 3277 3278 gpio-controller; 3279 #gpio-cells = <2>; 3280 gpio-ranges = <&pinctrl 0 160 32>; 3281 interrupt-controller; 3282 #interrupt-cells = <2>; 3283 }; 3284 3285 gpio6: gpio@21a00000 { 3286 compatible = "rockchip,gpio-bank"; 3287 reg = <0x21a00000 0x200>; 3288 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 3289 clocks = <&cru PCLK_GPIO6>, <&cru DBCLK_GPIO6>; 3290 3291 gpio-controller; 3292 #gpio-cells = <2>; 3293 gpio-ranges = <&pinctrl 0 192 32>; 3294 interrupt-controller; 3295 #interrupt-cells = <2>; 3296 }; 3297 3298 gpio7: gpio@21b00000 { 3299 compatible = "rockchip,gpio-bank"; 3300 reg = <0x21b00000 0x200>; 3301 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 3302 clocks = <&cru PCLK_GPIO7>, <&cru DBCLK_GPIO7>; 3303 3304 gpio-controller; 3305 #gpio-cells = <2>; 3306 gpio-ranges = <&pinctrl 0 224 32>; 3307 interrupt-controller; 3308 #interrupt-cells = <2>; 3309 }; 3310 }; 3311}; 3312 3313#include "rv1126b-pinctrl.dtsi" 3314
