1/* 2 * (C) Copyright 2025 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8 9/ { 10 aliases { 11 mmc0 = &emmc; 12 mmc1 = &sdmmc0; 13 }; 14 15 chosen { 16 stdout-path = &uart0; 17 u-boot,spl-boot-order = &sdmmc0, &spi_nand, &spi_nor, &emmc; 18 }; 19 20 secure-otp@20b10000 { 21 compatible = "rockchip,rv1126b-secure-otp"; 22 reg = <0x20b10000 0x10000>; 23 secure_conf = <0x2022001c>; 24 cru_rst_addr = <0x20200a00>; 25 mask_addr = <0x20ba0000>; 26 key_reader_addr = <0x20b20000>; 27 u-boot,dm-spl; 28 status = "okay"; 29 }; 30 31 crypto_s: crypto_s@20900000 { 32 compatible = "rockchip,crypto-ce"; 33 reg = <0x20900000 0x2000>; 34 secure; 35 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 36 clocks = <&cru ACLK_RKCE_S>, <&cru HCLK_RKCE_S>, 37 <&cru CLK_PKA_RKCE_S>; 38 clock-names = "aclk", "hclk", "pka"; 39 resets = <&cru SRST_PRESETN_RKCE>; 40 reset-names = "crypto-rst"; 41 status = "disabled"; 42 }; 43 44 keylad: keylad@20920000 { 45 compatible = "rockchip,keylad"; 46 reg = <0x20920000 0x2000>; 47 clocks = <&cru HCLK_KL_RKCE_S>, <&cru ACLK_RKCE_S>; 48 clock-names = "hclk", "aclk"; 49 status = "disabled"; 50 }; 51}; 52 53&gpio0 { 54 u-boot,dm-spl; 55 status = "okay"; 56}; 57 58&gpio1 { 59 u-boot,dm-pre-reloc; 60 status = "okay"; 61}; 62 63&gpio2 { 64 u-boot,dm-spl; 65 status = "okay"; 66}; 67 68&gpio3 { 69 u-boot,dm-pre-reloc; 70 status = "okay"; 71}; 72 73&gpio4 { 74 u-boot,dm-pre-reloc; 75 status = "okay"; 76}; 77 78&grf { 79 u-boot,dm-spl; 80 status = "okay"; 81}; 82 83&ioc_grf { 84 u-boot,dm-spl; 85 status = "okay"; 86}; 87 88&cru { 89 u-boot,dm-spl; 90 status = "okay"; 91}; 92 93&crypto { 94 u-boot,dm-spl; 95 status = "okay"; 96}; 97 98&crypto_s { 99 u-boot,dm-spl; 100 status = "okay"; 101}; 102 103&keylad { 104 u-boot,dm-spl; 105 status = "okay"; 106}; 107 108&psci { 109 u-boot,dm-pre-reloc; 110 status = "okay"; 111}; 112 113&uart0 { 114 u-boot,dm-spl; 115 status = "okay"; 116}; 117 118&hw_decompress { 119 u-boot,dm-spl; 120 status = "okay"; 121}; 122 123&rng { 124 u-boot,dm-pre-reloc; 125 status = "okay"; 126}; 127 128&fspi0 { 129 u-boot,dm-spl; 130 status = "okay"; 131 132 #address-cells = <1>; 133 #size-cells = <0>; 134 spi_nand: flash@0 { 135 u-boot,dm-spl; 136 compatible = "spi-nand"; 137 reg = <0>; 138 spi-tx-bus-width = <1>; 139 spi-rx-bus-width = <4>; 140 spi-max-frequency = <80000000>; 141 }; 142 143 spi_nor: flash@1 { 144 u-boot,dm-spl; 145 compatible = "jedec,spi-nor"; 146 label = "sfc_nor"; 147 reg = <0>; 148 spi-tx-bus-width = <1>; 149 spi-rx-bus-width = <4>; 150 spi-max-frequency = <80000000>; 151 }; 152}; 153 154&saradc0 { 155 u-boot,dm-pre-reloc; 156 status = "okay"; 157}; 158 159&sdmmc0 { 160 bus-width = <4>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&sdmmc0_bus4_pins &sdmmc0_cmd_pins &sdmmc0_clk_pins &sdmmc0_detn_pins>; 163 u-boot,dm-spl; 164 status = "okay"; 165}; 166 167&emmc { 168 mmc-ecsd = <0x47fffe00>; 169 mmc-idmac = <0x48000000>; 170 bus-width = <8>; 171 mmc-hs200-1_8v; 172 u-boot,dm-spl; 173 status = "okay"; 174}; 175 176&sdmmc0_pins { 177 u-boot,dm-spl; 178}; 179 180&sdmmc0_bus4_pins { 181 u-boot,dm-spl; 182}; 183 184&sdmmc0_cmd_pins { 185 u-boot,dm-spl; 186}; 187 188&sdmmc0_clk_pins { 189 u-boot,dm-spl; 190}; 191 192&sdmmc0_detn_pins { 193 u-boot,dm-spl; 194}; 195 196&pinctrl { 197 u-boot,dm-spl; 198 status = "okay"; 199}; 200 201&pcfg_pull_up { 202 u-boot,dm-spl; 203}; 204 205&pcfg_pull_none { 206 u-boot,dm-spl; 207}; 208 209&usb2phy { 210 u-boot,dm-pre-reloc; 211 status = "okay"; 212}; 213 214&usb2phy_otg { 215 u-boot,dm-pre-reloc; 216 status = "okay"; 217}; 218