1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rv1126-cru.h> 7#include <dt-bindings/power/rv1126-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/suspend/rockchip-rv1126.h> 15#include "rv1126-dram-default-timing.dtsi" 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 compatible = "rockchip,rv1126"; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 dphy0 = &csi_dphy0; 41 dphy1 = &csi_dphy1; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@f00 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a7"; 51 reg = <0xf00>; 52 enable-method = "psci"; 53 clocks = <&cru ARMCLK>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 cpu-idle-states = <&CPU_SLEEP>; 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 enable-method = "psci"; 63 clocks = <&cru ARMCLK>; 64 operating-points-v2 = <&cpu0_opp_table>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 }; 67 68 cpu2: cpu@f02 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a7"; 71 reg = <0xf02>; 72 enable-method = "psci"; 73 clocks = <&cru ARMCLK>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 cpu-idle-states = <&CPU_SLEEP>; 76 }; 77 78 cpu3: cpu@f03 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a7"; 81 reg = <0xf03>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 cpu-idle-states = <&CPU_SLEEP>; 86 }; 87 88 idle-states { 89 entry-method = "psci"; 90 91 CPU_SLEEP: cpu-sleep { 92 compatible = "arm,idle-state"; 93 local-timer-stop; 94 arm,psci-suspend-param = <0x0010000>; 95 entry-latency-us = <120>; 96 exit-latency-us = <250>; 97 min-residency-us = <900>; 98 }; 99 }; 100 101 }; 102 103 cpu0_opp_table: cpu0-opp-table { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 rockchip,reboot-freq = <816000>; 107 108 opp-408000000 { 109 opp-hz = /bits/ 64 <408000000>; 110 opp-microvolt = <725000 725000 1100000>; 111 clock-latency-ns = <40000>; 112 }; 113 opp-600000000 { 114 opp-hz = /bits/ 64 <600000000>; 115 opp-microvolt = <725000 725000 1000000>; 116 clock-latency-ns = <40000>; 117 }; 118 opp-816000000 { 119 opp-hz = /bits/ 64 <816000000>; 120 opp-microvolt = <725000 725000 1000000>; 121 clock-latency-ns = <40000>; 122 opp-suspend; 123 }; 124 opp-1008000000 { 125 opp-hz = /bits/ 64 <1008000000>; 126 opp-microvolt = <775000 775000 1000000>; 127 clock-latency-ns = <40000>; 128 }; 129 opp-1200000000 { 130 opp-hz = /bits/ 64 <1200000000>; 131 opp-microvolt = <825000 825000 1000000>; 132 clock-latency-ns = <40000>; 133 }; 134 opp-1296000000 { 135 opp-hz = /bits/ 64 <1296000000>; 136 opp-microvolt = <875000 875000 1000000>; 137 clock-latency-ns = <40000>; 138 }; 139 opp-1416000000 { 140 opp-hz = /bits/ 64 <1416000000>; 141 opp-microvolt = <925000 925000 1000000>; 142 clock-latency-ns = <40000>; 143 }; 144 opp-1512000000 { 145 opp-hz = /bits/ 64 <1512000000>; 146 opp-microvolt = <975000 975000 1000000>; 147 clock-latency-ns = <40000>; 148 }; 149 }; 150 151 arm-pmu { 152 compatible = "arm,cortex-a7-pmu"; 153 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 158 }; 159 160 bus_soc: bus-soc { 161 compatible = "rockchip,rv1126-bus"; 162 rockchip,busfreq-policy = "smc"; 163 soc-bus0 { 164 bus-id = <0>; 165 cfg-val = <0x00300020>; 166 enable-msk = <0x7144>; 167 status = "okay"; 168 }; 169 soc-bus1 { 170 bus-id = <1>; 171 cfg-val = <0x00300020>; 172 enable-msk = <0x70ff>; 173 status = "disabled"; 174 }; 175 soc-bus2 { 176 bus-id = <2>; 177 cfg-val = <0x00300020>; 178 enable-msk = <0x70ff>; 179 status = "disabled"; 180 }; 181 soc-bus3 { 182 bus-id = <3>; 183 cfg-val = <0x00300020>; 184 enable-msk = <0x70ff>; 185 status = "disabled"; 186 }; 187 soc-bus4 { 188 bus-id = <4>; 189 cfg-val = <0x00300020>; 190 enable-msk = <0x7011>; 191 status = "disabled"; 192 }; 193 soc-bus5 { 194 bus-id = <5>; 195 cfg-val = <0x00300020>; 196 enable-msk = <0x7011>; 197 status = "disabled"; 198 }; 199 soc-bus6 { 200 bus-id = <6>; 201 cfg-val = <0x00300020>; 202 enable-msk = <0x7011>; 203 status = "disabled"; 204 }; 205 soc-bus7 { 206 bus-id = <7>; 207 cfg-val = <0x00300020>; 208 enable-msk = <0x0>; 209 status = "disabled"; 210 }; 211 soc-bus8 { 212 bus-id = <8>; 213 cfg-val = <0x00300020>; 214 enable-msk = <0x0>; 215 status = "disabled"; 216 }; 217 soc-bus9 { 218 bus-id = <9>; 219 cfg-val = <0x00300020>; 220 enable-msk = <0x0>; 221 status = "disabled"; 222 }; 223 soc-bus10 { 224 bus-id = <10>; 225 cfg-val = <0x00300020>; 226 enable-msk = <0x0>; 227 status = "disabled"; 228 }; 229 soc-bus11 { 230 bus-id = <11>; 231 cfg-val = <0x00300020>; 232 enable-msk = <0x7000>; 233 status = "okey"; 234 }; 235 }; 236 237 display_subsystem: display-subsystem { 238 compatible = "rockchip,display-subsystem"; 239 ports = <&vop_out>; 240 status = "disabled"; 241 242 route { 243 route_dsi: route-dsi { 244 status = "disabled"; 245 logo,uboot = "logo.bmp"; 246 logo,kernel = "logo_kernel.bmp"; 247 logo,mode = "center"; 248 charge_logo,mode = "center"; 249 connect = <&vop_out_dsi>; 250 }; 251 252 route_rgb: route-rgb { 253 status = "disabled"; 254 logo,uboot = "logo.bmp"; 255 logo,kernel = "logo_kernel.bmp"; 256 logo,mode = "center"; 257 charge_logo,mode = "center"; 258 connect = <&vop_out_rgb>; 259 }; 260 }; 261 }; 262 263 fiq_debugger: fiq-debugger { 264 compatible = "rockchip,fiq-debugger"; 265 rockchip,serial-id = <2>; 266 rockchip,wake-irq = <0>; 267 rockchip,irq-mode-enable = <0>; 268 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 269 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 270 status = "disabled"; 271 }; 272 273 firmware { 274 optee: optee { 275 compatible = "linaro,optee-tz"; 276 method = "smc"; 277 status = "disabled"; 278 }; 279 }; 280 281 mpp_srv: mpp-srv { 282 compatible = "rockchip,mpp-service"; 283 rockchip,taskqueue-count = <3>; 284 rockchip,resetgroup-count = <3>; 285 status = "disabled"; 286 }; 287 288 psci { 289 compatible = "arm,psci-1.0"; 290 method = "smc"; 291 }; 292 293 reserved-memory { 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges; 297 298 isp_reserved: isp { 299 compatible = "shared-dma-pool"; 300 reusable; 301 size = <0x6800000>; 302 }; 303 304 ramoops: ramoops@8000000 { 305 compatible = "ramoops"; 306 reg = <0x8000000 0x100000>; 307 record-size = <0x20000>; 308 console-size = <0x40000>; 309 ftrace-size = <0x00000>; 310 pmsg-size = <0x40000>; 311 status = "disabled"; 312 }; 313 }; 314 315 rockchip_suspend: rockchip-suspend { 316 compatible = "rockchip,pm-rv1126"; 317 status = "disabled"; 318 rockchip,sleep-debug-en = <0>; 319 rockchip,sleep-mode-config = < 320 (0 321 | RKPM_SLP_ARMOFF 322 | RKPM_SLP_PMU_PMUALIVE_32K 323 | RKPM_SLP_PMU_DIS_OSC 324 | RKPM_SLP_PMIC_LP 325 ) 326 >; 327 rockchip,wakeup-config = < 328 (0 329 | RKPM_GPIO_WKUP_EN 330 ) 331 >; 332 }; 333 334 rockchip_system_monitor: rockchip-system-monitor { 335 compatible = "rockchip,system-monitor"; 336 }; 337 338 thermal_zones: thermal-zones { 339 cpu_thermal: cpu-thermal { 340 polling-delay-passive = <20>; /* milliseconds */ 341 polling-delay = <1000>; /* milliseconds */ 342 sustainable-power = <977>; /* milliwatts */ 343 344 thermal-sensors = <&cpu_tsadc 0>; 345 }; 346 347 npu_thermal: npu-thermal { 348 polling-delay-passive = <20>; /* milliseconds */ 349 polling-delay = <1000>; /* milliseconds */ 350 sustainable-power = <977>; /* milliwatts */ 351 352 thermal-sensors = <&npu_tsadc 0>; 353 }; 354 }; 355 356 timer { 357 compatible = "arm,armv7-timer"; 358 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 359 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 360 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 361 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 362 clock-frequency = <24000000>; 363 }; 364 365 xin24m: oscillator { 366 compatible = "fixed-clock"; 367 clock-frequency = <24000000>; 368 clock-output-names = "xin24m"; 369 #clock-cells = <0>; 370 }; 371 372 gmac_clkin_m0: external-gmac-clockm0 { 373 compatible = "fixed-clock"; 374 clock-frequency = <125000000>; 375 clock-output-names = "clk_gmac_rgmii_clkin_m0"; 376 #clock-cells = <0>; 377 }; 378 379 gmac_clkini_m1: external-gmac-clockm1 { 380 compatible = "fixed-clock"; 381 clock-frequency = <125000000>; 382 clock-output-names = "clk_gmac_rgmii_clkin_m1"; 383 #clock-cells = <0>; 384 }; 385 386 grf: syscon@fe000000 { 387 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 388 reg = <0xfe000000 0x20000>; 389 390 rgb: rgb { 391 compatible = "rockchip,rv1126-rgb"; 392 status = "disabled"; 393 394 ports { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 398 port@0 { 399 reg = <0>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 rgb_in_vop: endpoint@0 { 404 reg = <0>; 405 remote-endpoint = <&vop_out_rgb>; 406 }; 407 }; 408 409 }; 410 }; 411 }; 412 413 pmugrf: syscon@fe020000 { 414 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 415 reg = <0xfe020000 0x1000>; 416 417 pmu_io_domains: io-domains { 418 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 419 }; 420 421 reboot-mode { 422 compatible = "syscon-reboot-mode"; 423 offset = <0x200>; 424 mode-bootloader = <BOOT_BL_DOWNLOAD>; 425 mode-charge = <BOOT_CHARGING>; 426 mode-fastboot = <BOOT_FASTBOOT>; 427 mode-loader = <BOOT_BL_DOWNLOAD>; 428 mode-normal = <BOOT_NORMAL>; 429 mode-recovery = <BOOT_RECOVERY>; 430 mode-ums = <BOOT_UMS>; 431 }; 432 }; 433 434 qos_usb_host: qos@fe810000 { 435 compatible = "syscon"; 436 reg = <0xfe810000 0x20>; 437 }; 438 439 qos_usb_otg: qos@fe810080 { 440 compatible = "syscon"; 441 reg = <0xfe810080 0x20>; 442 }; 443 444 qos_npu: qos@fe850000 { 445 compatible = "syscon"; 446 reg = <0xfe850000 0x20>; 447 }; 448 449 qos_emmc: qos@fe860000 { 450 compatible = "syscon"; 451 reg = <0xfe860000 0x20>; 452 }; 453 454 qos_nandc: qos@fe860080 { 455 compatible = "syscon"; 456 reg = <0xfe860080 0x20>; 457 }; 458 459 qos_sfc: qos@fe860200 { 460 compatible = "syscon"; 461 reg = <0xfe860200 0x20>; 462 }; 463 464 qos_sdio: qos@fe86c000 { 465 compatible = "syscon"; 466 reg = <0xfe86c000 0x20>; 467 }; 468 469 qos_vepu_rd0: qos@fe870000 { 470 compatible = "syscon"; 471 reg = <0xfe870000 0x20>; 472 }; 473 474 qos_vepu_rd1: qos@fe870080 { 475 compatible = "syscon"; 476 reg = <0xfe870080 0x20>; 477 }; 478 479 qos_vepu_wr: qos@fe870100 { 480 compatible = "syscon"; 481 reg = <0xfe870100 0x20>; 482 }; 483 484 qos_ispp_m0: qos@fe880000 { 485 compatible = "syscon"; 486 reg = <0xfe880000 0x20>; 487 }; 488 489 qos_ispp_m1: qos@fe880080 { 490 compatible = "syscon"; 491 reg = <0xfe880080 0x20>; 492 }; 493 494 qos_isp: qos@fe890000 { 495 compatible = "syscon"; 496 reg = <0xfe890000 0x20>; 497 }; 498 499 qos_cif_lite: qos@fe890080 { 500 compatible = "syscon"; 501 reg = <0xfe890080 0x20>; 502 }; 503 504 qos_cif: qos@fe890100 { 505 compatible = "syscon"; 506 reg = <0xfe890100 0x20>; 507 }; 508 509 qos_iep: qos@fe8a0000 { 510 compatible = "syscon"; 511 reg = <0xfe8a0000 0x20>; 512 }; 513 514 qos_rga_rd: qos@fe8a0080 { 515 compatible = "syscon"; 516 reg = <0xfe8a0080 0x20>; 517 }; 518 519 qos_rga_wr: qos@fe8a0100 { 520 compatible = "syscon"; 521 reg = <0xfe8a0100 0x20>; 522 }; 523 524 qos_vop: qos@fe8a0180 { 525 compatible = "syscon"; 526 reg = <0xfe8a0180 0x20>; 527 }; 528 529 qos_vdpu: qos@fe8b0000 { 530 compatible = "syscon"; 531 reg = <0xfe8b0000 0x20>; 532 }; 533 534 qos_jpeg: qos@fe8c0000 { 535 compatible = "syscon"; 536 reg = <0xfe8c0000 0x20>; 537 }; 538 539 qos_crypto: qos@fe8d0000 { 540 compatible = "syscon"; 541 reg = <0xfe8d0000 0x20>; 542 }; 543 544 gic: interrupt-controller@feff0000 { 545 compatible = "arm,gic-400"; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 #address-cells = <0>; 549 550 reg = <0xfeff1000 0x1000>, 551 <0xfeff2000 0x2000>, 552 <0xfeff4000 0x2000>, 553 <0xfeff6000 0x2000>; 554 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 555 }; 556 557 arm-debug@ff010000 { 558 compatible = "rockchip,debug"; 559 reg = <0xff010000 0x1000>, 560 <0xff012000 0x1000>, 561 <0xff014000 0x1000>, 562 <0xff016000 0x1000>; 563 }; 564 565 pvtm@ff040000 { 566 compatible = "rockchip,rv1126-cpu-pvtm"; 567 reg = <0xff040000 0x100>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 571 pvtm@0 { 572 reg = <0>; 573 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>; 574 clock-names = "clk", "pclk"; 575 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>; 576 reset-names = "rst", "rst-p"; 577 }; 578 }; 579 580 pmu: power-management@ff3e0000 { 581 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 582 reg = <0xff3e0000 0x1000>; 583 584 power: power-controller { 585 compatible = "rockchip,rv1126-power-controller"; 586 #power-domain-cells = <1>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "okay"; 590 591 /* These power domains are grouped by VD_NPU */ 592 pd_npu@RV1126_PD_NPU { 593 reg = <RV1126_PD_NPU>; 594 clocks = <&cru ACLK_NPU>, 595 <&cru HCLK_NPU>, 596 <&cru PCLK_PDNPU>, 597 <&cru CLK_CORE_NPU>; 598 pm_qos = <&qos_npu>; 599 }; 600 /* These power domains are grouped by VD_VEPU */ 601 pd_vepu@RV1126_PD_VEPU { 602 reg = <RV1126_PD_VEPU>; 603 clocks = <&cru ACLK_VENC>, 604 <&cru HCLK_VENC>, 605 <&cru CLK_VENC_CORE>; 606 pm_qos = <&qos_vepu_rd0>, 607 <&qos_vepu_rd1>, 608 <&qos_vepu_wr>; 609 }; 610 /* These power domains are grouped by VD_LOGIC */ 611 pd_crypto@RV1126_PD_CRYPTO { 612 reg = <RV1126_PD_CRYPTO>; 613 clocks = <&cru ACLK_CRYPTO>, 614 <&cru HCLK_CRYPTO>, 615 <&cru CLK_CRYPTO_CORE>, 616 <&cru CLK_CRYPTO_PKA>; 617 pm_qos = <&qos_crypto>; 618 }; 619 pd_vi@RV1126_PD_VI { 620 reg = <RV1126_PD_VI>; 621 clocks = <&cru ACLK_ISP>, 622 <&cru HCLK_ISP>, 623 <&cru CLK_ISP>, 624 <&cru ACLK_CIF>, 625 <&cru HCLK_CIF>, 626 <&cru DCLK_CIF>, 627 <&cru CLK_CIF_OUT>, 628 <&cru CLK_MIPICSI_OUT>, 629 <&cru PCLK_CSIHOST>, 630 <&cru ACLK_CIFLITE>, 631 <&cru HCLK_CIFLITE>, 632 <&cru DCLK_CIFLITE>; 633 pm_qos = <&qos_isp>, 634 <&qos_cif_lite>, 635 <&qos_cif>; 636 }; 637 pd_vo@RV1126_PD_VO { 638 reg = <RV1126_PD_VO>; 639 clocks = <&cru ACLK_RGA>, 640 <&cru HCLK_RGA>, 641 <&cru CLK_RGA_CORE>, 642 <&cru ACLK_VOP>, 643 <&cru HCLK_VOP>, 644 <&cru DCLK_VOP>, 645 <&cru PCLK_DSIHOST>, 646 <&cru ACLK_IEP>, 647 <&cru HCLK_IEP>, 648 <&cru CLK_IEP_CORE>; 649 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 650 <&qos_vop>, <&qos_iep>; 651 }; 652 pd_ispp@RV1126_PD_ISPP { 653 reg = <RV1126_PD_ISPP>; 654 clocks = <&cru ACLK_ISPP>, 655 <&cru HCLK_ISPP>, 656 <&cru CLK_ISPP>; 657 pm_qos = <&qos_ispp_m0>, 658 <&qos_ispp_m1>; 659 }; 660 pd_vdpu@RV1126_PD_VDPU { 661 reg = <RV1126_PD_VDPU>; 662 clocks = <&cru ACLK_VDEC>, 663 <&cru HCLK_VDEC>, 664 <&cru CLK_VDEC_CORE>, 665 <&cru CLK_VDEC_CA>, 666 <&cru CLK_VDEC_HEVC_CA>, 667 <&cru ACLK_JPEG>, 668 <&cru HCLK_JPEG>; 669 pm_qos = <&qos_vdpu>, 670 <&qos_jpeg>; 671 }; 672 pd_nvm@RV1126_PD_NVM { 673 reg = <RV1126_PD_NVM>; 674 clocks = <&cru HCLK_EMMC>, 675 <&cru CLK_EMMC>, 676 <&cru HCLK_NANDC>, 677 <&cru CLK_NANDC>, 678 <&cru HCLK_SFC>, 679 <&cru HCLK_SFCXIP>, 680 <&cru SCLK_SFC>; 681 pm_qos = <&qos_emmc>, 682 <&qos_nandc>, 683 <&qos_sfc>; 684 }; 685 pd_sdio@RV1126_PD_SDIO { 686 reg = <RV1126_PD_SDIO>; 687 clocks = <&cru HCLK_SDIO>, 688 <&cru CLK_SDIO>; 689 pm_qos = <&qos_sdio>; 690 }; 691 pd_usb@RV1126_PD_USB { 692 reg = <RV1126_PD_USB>; 693 clocks = <&cru HCLK_USBHOST>, 694 <&cru HCLK_USBHOST_ARB>, 695 <&cru CLK_USBHOST_UTMI_OHCI>, 696 <&cru ACLK_USBOTG>, 697 <&cru CLK_USBOTG_REF>; 698 pm_qos = <&qos_usb_host>, 699 <&qos_usb_otg>; 700 }; 701 }; 702 }; 703 704 i2c0: i2c@ff3f0000 { 705 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 706 reg = <0xff3f0000 0x1000>; 707 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 711 clock-names = "i2c", "pclk"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&i2c0_xfer>; 714 status = "disabled"; 715 }; 716 717 i2c2: i2c@ff400000 { 718 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 719 reg = <0xff400000 0x1000>; 720 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 rockchip,grf = <&pmugrf>; 724 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; 725 clock-names = "i2c", "pclk"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&i2c2_xfer>; 728 status = "disabled"; 729 }; 730 731 amba { 732 compatible = "simple-bus"; 733 #address-cells = <1>; 734 #size-cells = <1>; 735 ranges; 736 737 dmac: dma-controller@ff4e0000 { 738 compatible = "arm,pl330", "arm,primecell"; 739 reg = <0xff4e0000 0x4000>; 740 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 742 #dma-cells = <1>; 743 clocks = <&cru ACLK_DMAC>; 744 clock-names = "apb_pclk"; 745 }; 746 }; 747 748 uart1: serial@ff410000 { 749 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 750 reg = <0xff410000 0x100>; 751 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 752 reg-shift = <2>; 753 reg-io-width = <4>; 754 dmas = <&dmac 7>, <&dmac 6>; 755 clock-frequency = <24000000>; 756 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 757 clock-names = "baudclk", "apb_pclk"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 760 status = "disabled"; 761 }; 762 763 pwm0: pwm@ff430000 { 764 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 765 reg = <0xff430000 0x10>; 766 #pwm-cells = <3>; 767 pinctrl-names = "active"; 768 pinctrl-0 = <&pwm0m0_pins>; 769 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 770 clock-names = "pwm", "pclk"; 771 status = "disabled"; 772 }; 773 774 pwm1: pwm@ff430010 { 775 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 776 reg = <0xff430010 0x10>; 777 #pwm-cells = <3>; 778 pinctrl-names = "active"; 779 pinctrl-0 = <&pwm1m0_pins>; 780 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 781 clock-names = "pwm", "pclk"; 782 status = "disabled"; 783 }; 784 785 pwm2: pwm@ff430020 { 786 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 787 reg = <0xff430020 0x10>; 788 #pwm-cells = <3>; 789 pinctrl-names = "active"; 790 pinctrl-0 = <&pwm2m0_pins>; 791 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 792 clock-names = "pwm", "pclk"; 793 status = "disabled"; 794 }; 795 796 pwm3: pwm@ff430030 { 797 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 798 reg = <0xff430030 0x10>; 799 #pwm-cells = <3>; 800 pinctrl-names = "active"; 801 pinctrl-0 = <&pwm3m0_pins>; 802 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 803 clock-names = "pwm", "pclk"; 804 status = "disabled"; 805 }; 806 807 pwm4: pwm@ff440000 { 808 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 809 reg = <0xff440000 0x10>; 810 #pwm-cells = <3>; 811 pinctrl-names = "active"; 812 pinctrl-0 = <&pwm4m0_pins>; 813 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 814 clock-names = "pwm", "pclk"; 815 status = "disabled"; 816 }; 817 818 pwm5: pwm@ff440010 { 819 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 820 reg = <0xff440010 0x10>; 821 #pwm-cells = <3>; 822 pinctrl-names = "active"; 823 pinctrl-0 = <&pwm5m0_pins>; 824 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 825 clock-names = "pwm", "pclk"; 826 status = "disabled"; 827 }; 828 829 pwm6: pwm@ff440020 { 830 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 831 reg = <0xff440020 0x10>; 832 #pwm-cells = <3>; 833 pinctrl-names = "active"; 834 pinctrl-0 = <&pwm6m0_pins>; 835 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 836 clock-names = "pwm", "pclk"; 837 status = "disabled"; 838 }; 839 840 pwm7: pwm@ff440030 { 841 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 842 reg = <0xff440030 0x10>; 843 #pwm-cells = <3>; 844 pinctrl-names = "active"; 845 pinctrl-0 = <&pwm7m0_pins>; 846 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 847 clock-names = "pwm", "pclk"; 848 status = "disabled"; 849 }; 850 851 spi0: spi@ff450000 { 852 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 853 reg = <0xff450000 0x1000>; 854 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 clocks = <&pmucru CLK_SPI0>, <&pmucru PCLK_SPI0>; 858 clock-names = "spiclk", "apb_pclk"; 859 dmas = <&dmac 1>, <&dmac 0>; 860 dma-names = "tx", "rx"; 861 pinctrl-names = "default", "high_speed"; 862 pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>; 863 pinctrl-1 = <&spi0m0_clk_hs &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso_hs &spi0m0_mosi_hs>; 864 status = "disabled"; 865 }; 866 867 pvtm@ff470000 { 868 compatible = "rockchip,rv1126-pmu-pvtm"; 869 reg = <0xff470000 0x100>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 pvtm@2 { 874 reg = <2>; 875 clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>; 876 clock-names = "clk", "pclk"; 877 resets = <&pmucru SRST_PMUPVTM>, 878 <&pmucru SRST_PMUPVTM_P>; 879 reset-names = "rst", "rst-p"; 880 }; 881 }; 882 883 pmucru: clock-controller@ff480000 { 884 compatible = "rockchip,rv1126-pmucru"; 885 reg = <0xff480000 0x1000>; 886 rockchip,grf = <&grf>; 887 #clock-cells = <1>; 888 #reset-cells = <1>; 889 }; 890 891 cru: clock-controller@ff490000 { 892 compatible = "rockchip,rv1126-cru"; 893 reg = <0xff490000 0x1000>; 894 rockchip,grf = <&grf>; 895 #clock-cells = <1>; 896 #reset-cells = <1>; 897 898 assigned-clocks = 899 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, 900 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, 901 <&cru PLL_HPLL>, <&cru ARMCLK>, 902 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, 903 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, 904 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, 905 <&cru HCLK_PDCORE_NIU>; 906 assigned-clock-rates = 907 <32768>, <1188000000>, 908 <100000000>, <500000000>, 909 <1400000000>, <600000000>, 910 <500000000>, <200000000>, 911 <100000000>, <300000000>, 912 <200000000>, <150000000>, 913 <200000000>; 914 assigned-clock-parents = 915 <&pmucru CLK_OSC0_DIV32K>; 916 }; 917 918 csi_dphy0: csi-dphy@ff4b0000 { 919 compatible = "rockchip,rv1126-csi-dphy"; 920 reg = <0xff4b0000 0x8000>; 921 clocks = <&cru PCLK_CSIPHY0>; 922 clock-names = "pclk"; 923 rockchip,grf = <&grf>; 924 status = "disabled"; 925 }; 926 927 csi_dphy1: csi-dphy@ff4b8000 { 928 compatible = "rockchip,rv1126-csi-dphy"; 929 reg = <0xff4b8000 0x8000>; 930 clocks = <&cru PCLK_CSIPHY1>; 931 clock-names = "pclk"; 932 rockchip,grf = <&grf>; 933 status = "disabled"; 934 }; 935 936 u2phy0: usb2-phy@ff4c0000 { 937 compatible = "rockchip,rv1126-usb2phy"; 938 reg = <0xff4c0000 0x8000>; 939 rockchip,grf = <&grf>; 940 clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>; 941 clock-names = "phyclk", "pclk"; 942 resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>; 943 reset-names = "u2phy", "u2phy-apb"; 944 #clock-cells = <0>; 945 status = "disabled"; 946 947 u2phy_otg: otg-port { 948 #phy-cells = <0>; 949 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "otg-bvalid", "otg-id", 954 "linestate", "disconnect"; 955 status = "disabled"; 956 }; 957 }; 958 959 u2phy1: usb2-phy@ff4c8000 { 960 compatible = "rockchip,rv1126-usb2phy"; 961 reg = <0xff4c8000 0x8000>; 962 rockchip,grf = <&grf>; 963 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>; 964 clock-names = "phyclk", "pclk"; 965 assigned-clocks = <&cru USB480M>; 966 assigned-clock-parents = <&u2phy1>; 967 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>; 968 reset-names = "u2phy", "u2phy-apb"; 969 #clock-cells = <0>; 970 clock-output-names = "usb480m_phy"; 971 status = "disabled"; 972 973 u2phy_host: host-port { 974 #phy-cells = <0>; 975 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 977 interrupt-names = "linestate", "disconnect"; 978 status = "disabled"; 979 }; 980 }; 981 982 mipi_dphy: mipi-dphy@ff4d0000 { 983 compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy"; 984 reg = <0xff4d0000 0x500>; 985 assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>; 986 assigned-clock-rates = <24000000>; 987 clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>; 988 clock-names = "ref", "pclk"; 989 clock-output-names = "mipi_dphy_pll"; 990 #clock-cells = <0>; 991 resets = <&cru SRST_DSIPHY_P>; 992 reset-names = "apb"; 993 #phy-cells = <0>; 994 rockchip,grf = <&grf>; 995 status = "disabled"; 996 }; 997 998 rng: rng@ff500000 { 999 compatible = "rockchip,cryptov2-rng"; 1000 reg = <0xff500000 0x4000>; 1001 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>, 1002 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1003 clock-names = "clk_crypto", "clk_crypto_apk", 1004 "aclk_crypto", "hclk_crypto"; 1005 assigned-clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>, 1006 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1007 assigned-clock-rates = <150000000>, <150000000>, 1008 <200000000>, <100000000>; 1009 power-domains = <&power RV1126_PD_CRYPTO>; 1010 resets = <&cru SRST_CRYPTO_CORE>; 1011 reset-names = "reset"; 1012 status = "disabled"; 1013 }; 1014 1015 i2c1: i2c@ff510000 { 1016 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1017 reg = <0xff510000 0x1000>; 1018 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1022 clock-names = "i2c", "pclk"; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&i2c1_xfer>; 1025 status = "disabled"; 1026 }; 1027 1028 i2c3: i2c@ff520000 { 1029 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1030 reg = <0xff520000 0x1000>; 1031 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1035 clock-names = "i2c", "pclk"; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&i2c3m0_xfer>; 1038 status = "disabled"; 1039 }; 1040 1041 i2c4: i2c@ff530000 { 1042 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1043 reg = <0xff530000 0x1000>; 1044 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1048 clock-names = "i2c", "pclk"; 1049 pinctrl-names = "default"; 1050 pinctrl-0 = <&i2c4m0_xfer>; 1051 status = "disabled"; 1052 }; 1053 1054 i2c5: i2c@ff540000 { 1055 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1056 reg = <0xff540000 0x1000>; 1057 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1061 clock-names = "i2c", "pclk"; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&i2c5m0_xfer>; 1064 status = "disabled"; 1065 }; 1066 1067 pwm8: pwm@ff550000 { 1068 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1069 reg = <0xff550000 0x10>; 1070 #pwm-cells = <3>; 1071 pinctrl-names = "active"; 1072 pinctrl-0 = <&pwm8m0_pins>; 1073 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1074 clock-names = "pwm", "pclk"; 1075 status = "disabled"; 1076 }; 1077 1078 pwm9: pwm@ff550010 { 1079 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1080 reg = <0xff550010 0x10>; 1081 #pwm-cells = <3>; 1082 pinctrl-names = "active"; 1083 pinctrl-0 = <&pwm9m0_pins>; 1084 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1085 clock-names = "pwm", "pclk"; 1086 status = "disabled"; 1087 }; 1088 1089 pwm10: pwm@ff550020 { 1090 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1091 reg = <0xff550020 0x10>; 1092 #pwm-cells = <3>; 1093 pinctrl-names = "active"; 1094 pinctrl-0 = <&pwm10m0_pins>; 1095 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1096 clock-names = "pwm", "pclk"; 1097 status = "disabled"; 1098 }; 1099 1100 pwm11: pwm@ff550030 { 1101 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1102 reg = <0xff550030 0x10>; 1103 #pwm-cells = <3>; 1104 pinctrl-names = "active"; 1105 pinctrl-0 = <&pwm11m0_pins>; 1106 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1107 clock-names = "pwm", "pclk"; 1108 status = "disabled"; 1109 }; 1110 1111 uart0: serial@ff560000 { 1112 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1113 reg = <0xff560000 0x100>; 1114 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1115 reg-shift = <2>; 1116 reg-io-width = <4>; 1117 dmas = <&dmac 5>, <&dmac 4>; 1118 clock-frequency = <24000000>; 1119 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1120 clock-names = "baudclk", "apb_pclk"; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; 1123 status = "disabled"; 1124 }; 1125 1126 uart2: serial@ff570000 { 1127 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1128 reg = <0xff570000 0x100>; 1129 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1130 reg-shift = <2>; 1131 reg-io-width = <4>; 1132 dmas = <&dmac 9>, <&dmac 8>; 1133 clock-frequency = <24000000>; 1134 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1135 clock-names = "baudclk", "apb_pclk"; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&uart2m1_xfer>; 1138 status = "disabled"; 1139 }; 1140 1141 uart3: serial@ff580000 { 1142 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1143 reg = <0xff580000 0x100>; 1144 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1145 reg-shift = <2>; 1146 reg-io-width = <4>; 1147 dmas = <&dmac 11>, <&dmac 10>; 1148 clock-frequency = <24000000>; 1149 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1150 clock-names = "baudclk", "apb_pclk"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>; 1153 status = "disabled"; 1154 }; 1155 1156 uart4: serial@ff590000 { 1157 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1158 reg = <0xff590000 0x100>; 1159 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1160 reg-shift = <2>; 1161 reg-io-width = <4>; 1162 dmas = <&dmac 13>, <&dmac 12>; 1163 clock-frequency = <24000000>; 1164 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1165 clock-names = "baudclk", "apb_pclk"; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; 1168 status = "disabled"; 1169 }; 1170 1171 uart5: serial@ff5a0000 { 1172 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1173 reg = <0xff5a0000 0x100>; 1174 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1175 reg-shift = <2>; 1176 reg-io-width = <4>; 1177 dmas = <&dmac 15>, <&dmac 14>; 1178 clock-frequency = <24000000>; 1179 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1180 clock-names = "baudclk", "apb_pclk"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 1183 status = "disabled"; 1184 }; 1185 1186 spi1: spi@ff5b0000 { 1187 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 1188 reg = <0xff5b0000 0x1000>; 1189 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1193 clock-names = "spiclk", "apb_pclk"; 1194 dmas = <&dmac 3>, <&dmac 2>; 1195 dma-names = "tx", "rx"; 1196 pinctrl-names = "default", "high_speed"; 1197 pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>; 1198 pinctrl-1 = <&spi1m0_clk_hs &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso_hs &spi1m0_mosi_hs>; 1199 status = "disabled"; 1200 }; 1201 1202 otp: otp@ff5c0000 { 1203 compatible = "rockchip,rv1126-otp"; 1204 reg = <0xff5c0000 0x1000>; 1205 #address-cells = <1>; 1206 #size-cells = <1>; 1207 clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>; 1208 clock-names = "otp", "apb_pclk"; 1209 status = "disabled"; 1210 1211 /* Data cells */ 1212 otp_id: id@7 { 1213 reg = <0x07 0x10>; 1214 }; 1215 cpu_leakage: cpu-leakage@17 { 1216 reg = <0x17 0x1>; 1217 }; 1218 logic_leakage: logic-leakage@18 { 1219 reg = <0x18 0x1>; 1220 }; 1221 npu_leakage: npu-leakage@19 { 1222 reg = <0x19 0x1>; 1223 }; 1224 }; 1225 1226 saradc: saradc@ff5e0000 { 1227 compatible = "rockchip,rk3399-saradc"; 1228 reg = <0xff5e0000 0x100>; 1229 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1230 #io-channel-cells = <1>; 1231 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1232 clock-names = "saradc", "apb_pclk"; 1233 resets = <&cru SRST_SARADC_P>; 1234 reset-names = "saradc-apb"; 1235 status = "disabled"; 1236 }; 1237 1238 cpu_tsadc: tsadc@ff5f0000 { 1239 compatible = "rockchip,rv1126-tsadc"; 1240 reg = <0xff5f0000 0x100>; 1241 rockchip,grf = <&grf>; 1242 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1243 assigned-clocks = <&cru CLK_CPU_TSADC>; 1244 assigned-clock-rates = <4000000>; 1245 clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>, 1246 <&cru CLK_CPU_TSADCPHY>; 1247 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1248 resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>, 1249 <&cru SRST_CPU_TSADCPHY>; 1250 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1251 rockchip,hw-tshut-temp = <120000>; 1252 #thermal-sensor-cells = <1>; 1253 status = "disabled"; 1254 }; 1255 1256 npu_tsadc: tsadc@ff5f8000 { 1257 compatible = "rockchip,rv1126-tsadc"; 1258 reg = <0xff5f8000 0x100>; 1259 rockchip,grf = <&grf>; 1260 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1261 assigned-clocks = <&cru CLK_NPU_TSADC>; 1262 assigned-clock-rates = <4000000>; 1263 clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>, 1264 <&cru CLK_NPU_TSADCPHY>; 1265 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1266 resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>, 1267 <&cru SRST_NPU_TSADCPHY>; 1268 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1269 rockchip,hw-tshut-temp = <120000>; 1270 #thermal-sensor-cells = <1>; 1271 status = "disabled"; 1272 }; 1273 1274 can: can@ff610000 { 1275 compatible = "rockchip,can-1.0"; 1276 reg = <0xff610000 0x100>; 1277 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1278 assigned-clocks = <&cru CLK_CAN>; 1279 assigned-clock-rates = <200000000>; 1280 clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>; 1281 clock-names = "baudclk", "apb_pclk"; 1282 resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>; 1283 reset-names = "can", "can-apb"; 1284 status = "disabled"; 1285 }; 1286 1287 rktimer: rktimer@ff660000 { 1288 compatible = "rockchip,rk3288-timer"; 1289 reg = <0xff660000 0x20>; 1290 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 1292 clock-names = "pclk", "timer"; 1293 }; 1294 1295 wdt: watchdog@ff680000 { 1296 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt"; 1297 reg = <0xff680000 0x100>; 1298 clocks = <&cru PCLK_WDT>; 1299 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1300 status = "disabled"; 1301 }; 1302 1303 mailbox: mailbox@ff6a0000 { 1304 compatible = "rockchip,rv1126-mailbox", 1305 "rockchip,rk3368-mailbox"; 1306 reg = <0xff6a0000 0x1000>; 1307 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&cru PCLK_MAILBOX>; 1309 clock-names = "pclk_mailbox"; 1310 #mbox-cells = <1>; 1311 status = "disabled"; 1312 }; 1313 1314 hw_decompress: decompress@ff6c0000 { 1315 compatible = "rockchip,hw-decompress"; 1316 reg = <0xff6c0000 0x1000>; 1317 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1319 clock-names = "aclk", "dclk", "pclk"; 1320 status = "disabled"; 1321 }; 1322 1323 i2s0_8ch: i2s@ff800000 { 1324 compatible = "rockchip,rv1126-i2s-tdm"; 1325 reg = <0xff800000 0x1000>; 1326 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>; 1328 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1329 dmas = <&dmac 20>, <&dmac 19>; 1330 dma-names = "tx", "rx"; 1331 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>; 1332 reset-names = "tx-m", "rx-m"; 1333 rockchip,cru = <&cru>; 1334 rockchip,grf = <&grf>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&i2s0m0_sclk_tx 1337 &i2s0m0_sclk_rx 1338 &i2s0m0_lrck_tx 1339 &i2s0m0_lrck_rx 1340 &i2s0m0_sdi0 1341 &i2s0m0_sdo0 1342 &i2s0m0_sdo1_sdi3 1343 &i2s0m0_sdo2_sdi2 1344 &i2s0m0_sdo3_sdi1>; 1345 status = "disabled"; 1346 }; 1347 1348 i2s1_2ch: i2s@ff810000 { 1349 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1350 reg = <0xff810000 0x1000>; 1351 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>; 1353 clock-names = "i2s_clk", "i2s_hclk"; 1354 dmas = <&dmac 22>, <&dmac 21>; 1355 dma-names = "tx", "rx"; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&i2s1m0_sclk 1358 &i2s1m0_lrck 1359 &i2s1m0_sdi 1360 &i2s1m0_sdo>; 1361 status = "disabled"; 1362 }; 1363 1364 i2s2_2ch: i2s@ff820000 { 1365 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1366 reg = <0xff820000 0x1000>; 1367 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1368 clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>; 1369 clock-names = "i2s_clk", "i2s_hclk"; 1370 dmas = <&dmac 24>, <&dmac 23>; 1371 dma-names = "tx", "rx"; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&i2s2m0_sclk 1374 &i2s2m0_lrck 1375 &i2s2m0_sdi 1376 &i2s2m0_sdo>; 1377 status = "disabled"; 1378 }; 1379 1380 pdm: pdm@ff830000 { 1381 compatible = "rockchip,rv1126-pdm", "rockchip,pdm"; 1382 reg = <0xff830000 0x1000>; 1383 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1384 clock-names = "pdm_clk", "pdm_hclk"; 1385 dmas = <&dmac 25>; 1386 dma-names = "rx"; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&pdmm0_clk 1389 &pdmm0_clk1 1390 &pdmm0_sdi0 1391 &pdmm0_sdi1 1392 &pdmm0_sdi2 1393 &pdmm0_sdi3>; 1394 status = "disabled"; 1395 }; 1396 1397 audpwm: audpwm@ff840000 { 1398 compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1"; 1399 reg = <0xff840000 0x1000>; 1400 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 1401 clock-names = "clk", "hclk"; 1402 dmas = <&dmac 26>; 1403 dma-names = "tx"; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&audpwmm0_pins>; 1406 rockchip,sample-width-bits = <11>; 1407 rockchip,interpolat-points = <1>; 1408 status = "disabled"; 1409 }; 1410 1411 dfi: dfi@ff9c0000 { 1412 reg = <0xff9c0000 0x400>; 1413 compatible = "rockchip,rv1126-dfi"; 1414 rockchip,pmugrf = <&pmugrf>; 1415 status = "disabled"; 1416 }; 1417 1418 dmc: dmc { 1419 compatible = "rockchip,rv1126-dmc"; 1420 devfreq-events = <&dfi>; 1421 clocks = <&cru SCLK_DDRCLK>; 1422 clock-names = "dmc_clk"; 1423 operating-points-v2 = <&dmc_opp_table>; 1424 ddr_timing = <&ddr_timing>; 1425 upthreshold = <40>; 1426 downdifferential = <20>; 1427 system-status-freq = < 1428 /*system status freq(KHz)*/ 1429 SYS_STATUS_NORMAL 924000 1430 SYS_STATUS_REBOOT 450000 1431 SYS_STATUS_SUSPEND 328000 1432 SYS_STATUS_VIDEO_1080P 924000 1433 SYS_STATUS_BOOST 924000 1434 SYS_STATUS_ISP 924000 1435 SYS_STATUS_PERFORMANCE 924000 1436 >; 1437 auto-min-freq = <328000>; 1438 auto-freq-en = <0>; 1439 #cooling-cells = <2>; 1440 status = "disabled"; 1441 }; 1442 1443 dmc_opp_table: dmc-opp-table { 1444 compatible = "operating-points-v2"; 1445 1446 opp-328000000 { 1447 opp-hz = /bits/ 64 <328000000>; 1448 opp-microvolt = <800000>; 1449 }; 1450 opp-450000000 { 1451 opp-hz = /bits/ 64 <450000000>; 1452 opp-microvolt = <800000>; 1453 }; 1454 opp-664000000 { 1455 opp-hz = /bits/ 64 <664000000>; 1456 opp-microvolt = <800000>; 1457 }; 1458 opp-924000000 { 1459 opp-hz = /bits/ 64 <924000000>; 1460 opp-microvolt = <800000>; 1461 }; 1462 opp-1056000000 { 1463 opp-hz = /bits/ 64 <1056000000>; 1464 opp-microvolt = <800000>; 1465 status = "disabled"; 1466 }; 1467 }; 1468 1469 rkcif: rkcif@ffae0000 { 1470 compatible = "rockchip,rv1126-cif"; 1471 reg = <0xffae0000 0x10000>; 1472 reg-names = "cif_regs"; 1473 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1474 interrupt-names = "cif-intr"; 1475 clocks = <&cru ACLK_CIF>, <&cru ACLK_CIFLITE>, 1476 <&cru HCLK_CIF>, <&cru HCLK_CIFLITE>, 1477 <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>; 1478 clock-names = "aclk_cif", "aclk_cif_lite", 1479 "hclk_cif", "hclk_cif_lite", 1480 "dclk_cif", "dclk_cif_lite"; 1481 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, 1482 <&cru SRST_CIF_D>, <&cru SRST_CIF_P>, 1483 <&cru SRST_CIF_I>, <&cru SRST_CIF_RX_P>, 1484 <&cru SRST_CIFLITE_A>, <&cru SRST_CIFLITE_H>, 1485 <&cru SRST_CIFLITE_D>, <&cru SRST_CIFLITE_RX_P>; 1486 reset-names = "rst_cif_a", "rst_cif_h", 1487 "rst_cif_d", "rst_cif_p", 1488 "rst_cif_i", "rst_cif_rx_p", 1489 "rst_cif_lite_a", "rst_cif_lite_h", 1490 "rst_cif_lite_d", "rst_cif_lite_rx_p"; 1491 assigned-clocks = <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>; 1492 assigned-clock-rates = <300000000>, <300000000>; 1493 power-domains = <&power RV1126_PD_VI>; 1494 iommus = <&rkcif_mmu>; 1495 status = "disabled"; 1496 }; 1497 1498 rkcif_mmu: iommu@ffae0800 { 1499 compatible = "rockchip,iommu"; 1500 reg = <0xffae0800 0x100>; 1501 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1502 interrupt-names = "cif_mmu"; 1503 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1504 clock-names = "aclk", "hclk"; 1505 power-domains = <&power RV1126_PD_VI>; 1506 #iommu-cells = <0>; 1507 status = "disabled"; 1508 }; 1509 1510 rk_rga: rk_rga@ffaf0000 { 1511 compatible = "rockchip,rga2"; 1512 reg = <0xffaf0000 0x1000>; 1513 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 1515 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1516 power-domains = <&power RV1126_PD_VO>; 1517 dma-coherent; 1518 status = "disable"; 1519 }; 1520 1521 vop: vop@ffb00000 { 1522 compatible = "rockchip,rv1126-vop"; 1523 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 1524 reg-names = "regs", "gamma_lut"; 1525 rockchip,grf = <&grf>; 1526 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 1528 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1529 iommus = <&vop_mmu>; 1530 power-domains = <&power RV1126_PD_VO>; 1531 status = "disabled"; 1532 1533 vop_out: port { 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 1537 vop_out_rgb: endpoint@0 { 1538 reg = <0>; 1539 remote-endpoint = <&rgb_in_vop>; 1540 }; 1541 1542 vop_out_dsi: endpoint@1 { 1543 reg = <1>; 1544 remote-endpoint = <&dsi_in_vop>; 1545 }; 1546 }; 1547 }; 1548 1549 vop_mmu: iommu@ffb00f00 { 1550 compatible = "rockchip,iommu"; 1551 reg = <0xffb00f00 0x100>; 1552 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1553 interrupt-names = "vop_mmu"; 1554 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1555 clock-names = "aclk", "iface"; 1556 #iommu-cells = <0>; 1557 rockchip,disable-device-link-resume; 1558 power-domains = <&power RV1126_PD_VO>; 1559 status = "disabled"; 1560 }; 1561 1562 mipi_csi2: mipi-csi2@ffb10000 { 1563 compatible = "rockchip,rv1126-mipi-csi2"; 1564 reg = <0xffb10000 0x10000>; 1565 reg-names = "csihost_regs"; 1566 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1568 interrupt-names = "csi-intr1", "csi-intr2"; 1569 clocks = <&cru PCLK_CSIHOST>, <&cru SRST_CSIHOST_P>; 1570 clock-names = "pclk_csi2host", "srst_csihost_p"; 1571 power-domains = <&power RV1126_PD_VI>; 1572 status = "disabled"; 1573 }; 1574 1575 dsi: dsi@ffb30000 { 1576 compatible = "rockchip,rv1126-mipi-dsi"; 1577 reg = <0xffb30000 0x500>; 1578 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1579 clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>; 1580 clock-names = "pclk", "hs_clk"; 1581 resets = <&cru SRST_DSIHOST_P>; 1582 reset-names = "apb"; 1583 phys = <&mipi_dphy>; 1584 phy-names = "mipi_dphy"; 1585 rockchip,grf = <&grf>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 power-domains = <&power RV1126_PD_VO>; 1589 status = "disabled"; 1590 1591 ports { 1592 port { 1593 dsi_in_vop: endpoint { 1594 remote-endpoint = <&vop_out_dsi>; 1595 }; 1596 }; 1597 }; 1598 }; 1599 1600 rkisp: rkisp@ffb50000 { 1601 compatible = "rockchip,rv1126-rkisp"; 1602 reg = <0xffb50000 0x10000>; 1603 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1606 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1607 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1608 <&cru CLK_ISP>; 1609 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1610 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1611 assigned-clock-rates = <500000000>, <250000000>; 1612 power-domains = <&power RV1126_PD_VI>; 1613 /* iommus = <&rkisp_mmu>; */ 1614 memory-region = <&isp_reserved>; 1615 status = "disabled"; 1616 }; 1617 1618 rkisp_mmu: iommu@ffb51a00 { 1619 compatible = "rockchip,iommu"; 1620 reg = <0xffb51a00 0x100>; 1621 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1622 interrupt-names = "isp_mmu"; 1623 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1624 clock-names = "aclk", "iface"; 1625 power-domains = <&power RV1126_PD_VI>; 1626 #iommu-cells = <0>; 1627 rockchip,disable-mmu-reset; 1628 status = "disabled"; 1629 }; 1630 1631 rkispp: rkispp@ffb60000 { 1632 compatible = "rockchip,rv1126-rkispp"; 1633 reg = <0xffb60000 0x20000>; 1634 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1636 interrupt-names = "ispp_irq", "fec_irq"; 1637 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 1638 <&cru CLK_ISPP>; 1639 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 1640 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 1641 <&cru CLK_ISPP>; 1642 assigned-clock-rates = <500000000>, <250000000>, 1643 <400000000>; 1644 power-domains = <&power RV1126_PD_ISPP>; 1645 iommus = <&rkispp_mmu>; 1646 status = "disabled"; 1647 }; 1648 1649 rkispp_mmu: iommu@ffb60e00 { 1650 compatible = "rockchip,iommu"; 1651 reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>; 1652 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1655 interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1"; 1656 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>; 1657 clock-names = "aclk", "iface"; 1658 power-domains = <&power RV1126_PD_ISPP>; 1659 #iommu-cells = <0>; 1660 rockchip,disable-mmu-reset; 1661 status = "disabled"; 1662 }; 1663 1664 rkvdec: rkvdec@ffb80000 { 1665 compatible = "rockchip,rkv-decoder-v1"; 1666 reg = <0xffb80000 0x400>; 1667 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1668 interrupt-names = "irq_dec"; 1669 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>, 1670 <&cru CLK_VDEC_CA>, <&cru CLK_VDEC_CORE>, 1671 <&cru CLK_VDEC_HEVC_CA>; 1672 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", 1673 "clk_core", "clk_hevc_cabac"; 1674 resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>, 1675 <&cru SRST_VDEC_CA>, <&cru SRST_VDEC_CORE>, 1676 <&cru SRST_VDEC_HEVC_CA>; 1677 reset-names = "video_a", "video_h", "video_cabac", 1678 "video_core", "video_hevc_cabac"; 1679 power-domains = <&power RV1126_PD_VDPU>; 1680 iommus = <&rkvdec_mmu>; 1681 rockchip,srv = <&mpp_srv>; 1682 rockchip,taskqueue-node = <0>; 1683 rockchip,resetgroup-node = <0>; 1684 status = "disabled"; 1685 }; 1686 1687 rkvdec_mmu: iommu@ffb80480 { 1688 compatible = "rockchip,iommu"; 1689 reg = <0xffb80480 0x40>, <0xffb804c0 0x40>; 1690 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1691 interrupt-names = "rkvdec_mmu"; 1692 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>; 1693 clock-names = "aclk", "iface"; 1694 power-domains = <&power RV1126_PD_VDPU>; 1695 #iommu-cells = <0>; 1696 status = "disabled"; 1697 }; 1698 1699 vepu: vepu@ffb90000 { 1700 compatible = "rockchip,vpu-encoder-v2"; 1701 reg = <0xffb90000 0x400>; 1702 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1703 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 1704 clock-names = "aclk_vcodec", "hclk_vcodec"; 1705 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>; 1706 reset-names = "shared_video_a", "shared_video_h"; 1707 iommus = <&vpu_mmu>; 1708 rockchip,srv = <&mpp_srv>; 1709 rockchip,taskqueue-node = <1>; 1710 rockchip,resetgroup-node = <1>; 1711 power-domains = <&power RV1126_PD_VDPU>; 1712 status = "disabled"; 1713 }; 1714 1715 vdpu: vdpu@ffb90400 { 1716 compatible = "rockchip,vpu-decoder-v2"; 1717 reg = <0xffb90400 0x400>; 1718 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1719 interrupt-names = "irq_dec"; 1720 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 1721 clock-names = "aclk_vcodec", "hclk_vcodec"; 1722 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>; 1723 reset-names = "shared_video_a", "shared_video_h"; 1724 iommus = <&vpu_mmu>; 1725 power-domains = <&power RV1126_PD_VDPU>; 1726 rockchip,srv = <&mpp_srv>; 1727 rockchip,taskqueue-node = <1>; 1728 rockchip,resetgroup-node = <1>; 1729 status = "disabled"; 1730 }; 1731 1732 vpu_mmu: iommu@ffb90800 { 1733 compatible = "rockchip,iommu"; 1734 reg = <0xffb90800 0x40>; 1735 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1736 interrupt-names = "vpu_mmu"; 1737 clock-names = "aclk", "iface"; 1738 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 1739 power-domains = <&power RV1126_PD_VDPU>; 1740 #iommu-cells = <0>; 1741 status = "disabled"; 1742 }; 1743 1744 rkvenc: rkvenc@ffbb0000 { 1745 compatible = "rockchip,rkv-encoder-v1"; 1746 reg = <0xffbb0000 0x400>; 1747 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1748 interrupt-names = "irq_enc"; 1749 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>, 1750 <&cru CLK_VENC_CORE>; 1751 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1752 resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>, 1753 <&cru SRST_VENC_CORE>; 1754 reset-names = "video_a", "video_h", "video_core"; 1755 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>; 1756 assigned-clock-rates = <297000000>, <594000000>; 1757 operating-points-v2 = <&rkvenc_opp_table>; 1758 iommus = <&rkvenc_mmu>; 1759 node-name = "rkvenc"; 1760 rockchip,srv = <&mpp_srv>; 1761 rockchip,taskqueue-node = <2>; 1762 rockchip,resetgroup-node = <2>; 1763 power-domains = <&power RV1126_PD_VEPU>; 1764 status = "disabled"; 1765 }; 1766 1767 rkvenc_opp_table: rkvenc-opp-table { 1768 compatible = "operating-points-v2"; 1769 1770 /* The source clock is CLK_VENC_CORE */ 1771 opp-297000000 { 1772 opp-hz = /bits/ 64 <297000000>; 1773 opp-microvolt = <725000 725000 1000000>; 1774 }; 1775 opp-396000000 { 1776 opp-hz = /bits/ 64 <396000000>; 1777 opp-microvolt = <725000 725000 1000000>; 1778 }; 1779 opp-500000000 { 1780 opp-hz = /bits/ 64 <500000000>; 1781 opp-microvolt = <750000 750000 1000000>; 1782 }; 1783 opp-594000000 { 1784 opp-hz = /bits/ 64 <594000000>; 1785 opp-microvolt = <800000 800000 1000000>; 1786 }; 1787 }; 1788 1789 rkvenc_mmu: iommu@ffbb0f00 { 1790 compatible = "rockchip,iommu"; 1791 reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>; 1792 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1794 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 1795 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>; 1796 clock-names = "aclk", "iface"; 1797 rockchip,disable-mmu-reset; 1798 #iommu-cells = <0>; 1799 power-domains = <&power RV1126_PD_VEPU>; 1800 status = "disabled"; 1801 }; 1802 1803 pvtm@ffc00000 { 1804 compatible = "rockchip,rv1126-npu-pvtm"; 1805 reg = <0xffc00000 0x100>; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 1809 pvtm@1 { 1810 reg = <1>; 1811 clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>; 1812 clock-names = "clk", "pclk"; 1813 resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>; 1814 reset-names = "rts", "rst-p"; 1815 }; 1816 }; 1817 1818 gmac: ethernet@ffc40000 { 1819 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 1820 reg = <0xffc40000 0x0ffff>; 1821 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1823 interrupt-names = "macirq", "eth_wake_irq"; 1824 rockchip,grf = <&grf>; 1825 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 1826 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 1827 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 1828 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 1829 clock-names = "stmmaceth", "mac_clk_rx", 1830 "mac_clk_tx", "clk_mac_refout", 1831 "aclk_mac", "pclk_mac", 1832 "clk_mac_speed", "ptp_ref"; 1833 resets = <&cru SRST_GMAC_A>; 1834 reset-names = "stmmaceth"; 1835 1836 snps,mixed-burst; 1837 snps,tso; 1838 1839 snps,axi-config = <&stmmac_axi_setup>; 1840 snps,mtl-rx-config = <&mtl_rx_setup>; 1841 snps,mtl-tx-config = <&mtl_tx_setup>; 1842 status = "disabled"; 1843 1844 mdio: mdio { 1845 compatible = "snps,dwmac-mdio"; 1846 #address-cells = <0x1>; 1847 #size-cells = <0x0>; 1848 }; 1849 1850 stmmac_axi_setup: stmmac-axi-config { 1851 snps,wr_osr_lmt = <4>; 1852 snps,rd_osr_lmt = <8>; 1853 snps,blen = <0 0 0 0 16 8 4>; 1854 }; 1855 1856 mtl_rx_setup: rx-queues-config { 1857 snps,rx-queues-to-use = <1>; 1858 queue0 {}; 1859 }; 1860 1861 mtl_tx_setup: tx-queues-config { 1862 snps,tx-queues-to-use = <1>; 1863 queue0 {}; 1864 }; 1865 }; 1866 1867 emmc: dwmmc@ffc50000 { 1868 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1869 reg = <0xffc50000 0x4000>; 1870 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1871 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 1872 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1873 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1874 fifo-depth = <0x100>; 1875 max-frequency = <200000000>; 1876 pinctrl-names = "default"; 1877 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1878 power-domains = <&power RV1126_PD_NVM>; 1879 rockchip,use-v2-tuning; 1880 status = "disabled"; 1881 }; 1882 1883 sdmmc: dwmmc@ffc60000 { 1884 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1885 reg = <0xffc60000 0x4000>; 1886 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1887 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 1888 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1889 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1890 fifo-depth = <0x100>; 1891 max-frequency = <200000000>; 1892 pinctrl-names = "default"; 1893 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 1894 status = "disabled"; 1895 }; 1896 1897 sdio: dwmmc@ffc70000 { 1898 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1899 reg = <0xffc70000 0x4000>; 1900 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 1902 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1903 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1904 fifo-depth = <0x100>; 1905 max-frequency = <200000000>; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1908 power-domains = <&power RV1126_PD_SDIO>; 1909 status = "disabled"; 1910 }; 1911 1912 nandc: nandc@ffc80000 { 1913 compatible = "rockchip,rk-nandc"; 1914 reg = <0xffc80000 0x4000>; 1915 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1916 nandc_id = <0>; 1917 clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>; 1918 clock-names = "clk_nandc", "hclk_nandc"; 1919 pinctrl-names = "default"; 1920 pinctrl-0 = <&flash_pins>; 1921 power-domains = <&power RV1126_PD_NVM>; 1922 status = "disabled"; 1923 }; 1924 1925 sfc: sfc@ffc90000 { 1926 compatible = "rockchip,sfc"; 1927 reg = <0xffc90000 0x4000>; 1928 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1929 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1930 clock-names = "clk_sfc", "hclk_sfc"; 1931 assigned-clocks = <&cru SCLK_SFC>; 1932 assigned-clock-rates = <80000000>; 1933 power-domains = <&power RV1126_PD_NVM>; 1934 status = "disabled"; 1935 }; 1936 1937 npu: npu@ffbc0000 { 1938 compatible = "rockchip,npu"; 1939 reg = <0xffbc0000 0x4000>; 1940 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, <&cru PCLK_PDNPU>, <&cru CLK_CORE_NPU>; 1941 clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu"; 1942 assigned-clocks = <&cru CLK_CORE_NPU>; 1943 assigned-clock-rates = <396000000>; 1944 operating-points-v2 = <&npu_opp_table>; 1945 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1946 power-domains = <&power RV1126_PD_NPU>; 1947 status = "disabled"; 1948 }; 1949 1950 npu_opp_table: npu-opp-table { 1951 compatible = "operating-points-v2"; 1952 1953 opp-200000000 { 1954 opp-hz = /bits/ 64 <200000000>; 1955 opp-microvolt = <725000 725000 1000000>; 1956 }; 1957 opp-300000000 { 1958 opp-hz = /bits/ 64 <300000000>; 1959 opp-microvolt = <725000 725000 1000000>; 1960 }; 1961 opp-396000000 { 1962 opp-hz = /bits/ 64 <396000000>; 1963 opp-microvolt = <725000 725000 1000000>; 1964 }; 1965 opp-500000000 { 1966 opp-hz = /bits/ 64 <500000000>; 1967 opp-microvolt = <725000 725000 1000000>; 1968 }; 1969 opp-600000000 { 1970 opp-hz = /bits/ 64 <600000000>; 1971 opp-microvolt = <725000 725000 1000000>; 1972 }; 1973 opp-700000000 { 1974 opp-hz = /bits/ 64 <700000000>; 1975 opp-microvolt = <775000 775000 1000000>; 1976 }; 1977 opp-800000000 { 1978 opp-hz = /bits/ 64 <800000000>; 1979 opp-microvolt = <825000 825000 1000000>; 1980 }; 1981 }; 1982 1983 usbdrd: usb0 { 1984 compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3"; 1985 #address-cells = <1>; 1986 #size-cells = <1>; 1987 ranges; 1988 clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>, 1989 <&cru HCLK_PDUSB>; 1990 clock-names = "ref_clk", "bus_clk", "hclk"; 1991 status = "disabled"; 1992 1993 usbdrd_dwc3: dwc3@ffd00000 { 1994 compatible = "snps,dwc3"; 1995 reg = <0xffd00000 0x100000>; 1996 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1997 dr_mode = "otg"; 1998 maximum-speed = "high-speed"; 1999 phys = <&u2phy_otg>; 2000 phy-names = "usb2-phy"; 2001 phy_type = "utmi_wide"; 2002 power-domains = <&power RV1126_PD_USB>; 2003 resets = <&cru SRST_USBOTG_A>; 2004 reset-names = "usb3-otg"; 2005 snps,dis_enblslpm_quirk; 2006 snps,dis-u2-freeclk-exists-quirk; 2007 snps,dis_u2_susphy_quirk; 2008 snps,dis-del-phy-power-chg-quirk; 2009 snps,tx-ipgap-linecheck-dis-quirk; 2010 snps,xhci-trb-ent-quirk; 2011 status = "disabled"; 2012 }; 2013 }; 2014 2015 usb_host0_ehci: usb@ffe00000 { 2016 compatible = "generic-ehci"; 2017 reg = <0xffe00000 0x10000>; 2018 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2019 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 2020 <&u2phy1>; 2021 clock-names = "usbhost", "arbiter", "utmi"; 2022 phys = <&u2phy_host>; 2023 phy-names = "usb"; 2024 power-domains = <&power RV1126_PD_USB>; 2025 status = "disabled"; 2026 }; 2027 2028 usb_host0_ohci: usb@ffe10000 { 2029 compatible = "generic-ohci"; 2030 reg = <0xffe10000 0x10000>; 2031 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2032 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 2033 <&u2phy1>; 2034 clock-names = "usbhost", "arbiter", "utmi"; 2035 phys = <&u2phy_host>; 2036 phy-names = "usb"; 2037 power-domains = <&power RV1126_PD_USB>; 2038 status = "disabled"; 2039 }; 2040 2041 pinctrl: pinctrl { 2042 compatible = "rockchip,rv1126-pinctrl"; 2043 rockchip,grf = <&grf>; 2044 rockchip,pmu = <&pmugrf>; 2045 #address-cells = <1>; 2046 #size-cells = <1>; 2047 ranges; 2048 2049 gpio0: gpio0@ff460000 { 2050 compatible = "rockchip,gpio-bank"; 2051 reg = <0xff460000 0x100>; 2052 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2053 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 2054 2055 gpio-controller; 2056 #gpio-cells = <2>; 2057 2058 interrupt-controller; 2059 #interrupt-cells = <2>; 2060 }; 2061 2062 gpio1: gpio1@ff620000 { 2063 compatible = "rockchip,gpio-bank"; 2064 reg = <0xff620000 0x100>; 2065 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2066 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2067 2068 gpio-controller; 2069 #gpio-cells = <2>; 2070 2071 interrupt-controller; 2072 #interrupt-cells = <2>; 2073 }; 2074 2075 gpio2: gpio2@ff630000 { 2076 compatible = "rockchip,gpio-bank"; 2077 reg = <0xff630000 0x100>; 2078 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2079 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2080 2081 gpio-controller; 2082 #gpio-cells = <2>; 2083 2084 interrupt-controller; 2085 #interrupt-cells = <2>; 2086 }; 2087 2088 gpio3: gpio3@ff640000 { 2089 compatible = "rockchip,gpio-bank"; 2090 reg = <0xff640000 0x100>; 2091 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2092 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2093 2094 gpio-controller; 2095 #gpio-cells = <2>; 2096 2097 interrupt-controller; 2098 #interrupt-cells = <2>; 2099 }; 2100 2101 gpio4: gpio4@ff650000 { 2102 compatible = "rockchip,gpio-bank"; 2103 reg = <0xff650000 0x100>; 2104 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2105 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2106 2107 gpio-controller; 2108 #gpio-cells = <2>; 2109 2110 interrupt-controller; 2111 #interrupt-cells = <2>; 2112 }; 2113 }; 2114}; 2115 2116#include "rv1126-pinctrl.dtsi" 2117 2118
